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data sheet, rev. 1.31, dec. 2005 communications samurai 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996lcx - green package version; adm6996lhx - heat sink and green package) version ac
edition 2005-12-05 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: template_a4_3.1.fm / 3.1 / 2005-11-01 trademarks abm ? , aop ? , bluemoon ? , convergate ? , c166 ? , duslic ? , falc ? , geminax ? , inca ? , iom ? , ipvd ? , isac ? , iwe ? , iworx ? , muslic ? , octalfalc ? , octat ? , quadfalc ? , scout ? , serocco ? , s-gold ? , sicofi ? , sieget ? , smarti ? , socrates ? , vinetic ? , wdtc ? , 10bases ? are registered trademarks of infineon technologies ag. ace?, arcofi?, asm?, asp?, bluenix?, digitape?, dualfalc?, easyport?, e-gold?, e-goldlite?, epic?, ipat-2?, elic?, idec?, itac?, m-gold?, sct?, s-gold2?, s-gold3?, musac?, potswire?, quat?, s-goldlite?, sicat?, sidec?, slicofi?, vdslite?, 10basev?, 10basevx? are trademarks of infineon technologies ag. microsoft ? and visio ? are registered trademarks of microsoft corporation. linux ? is a registered trademark of linus torvalds. framemaker ? is a registered trademark of adobe systems incorporated. apoxi ? is a registered trademark of comneon gmbh & co. ohg. primecell ? , realview ? , arm ? are registered trademarks of arm limited. oakdspcore ? , teaklite ? dsp core, ocem ? are registered trademarks of parthusceva inc. indoorgps?, gl-20000?, gl-ln-22? are trademarks of global locate. arm926ej-s?, ads?, multi-ice? are trademarks of arm limited. samurai 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996lcx - green package version) revision history: 2005-12-05, rev. 1.31 previous version: 2005-04-28, rev.1.1 page/ date subjects (major changes since last revision) page19 modify lnkfp5 pin description page 71~156 add 16bits mode registers description 2005-08-30 changed to the new infineon format 2005-08-30 rev. 1.1 changed to rev. 1.3 update in content 2005-11-07 revision 1.3 changed to revision 1.31minor change. included green package information and heat sind information
data sheet 4 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pin description by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 100base-x module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 100base-x receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.1 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 adaptive equalizer and timing recovery module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.3 nrzi/nrz and serial/parallel decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 data de-scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.5 symbol alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.6 symbol decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.7 valid data signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.8 receive errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.9 100base-x link monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.10 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.11 bad ssd detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.12 far-end fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 100base-tx transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.1 transmit drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.2 twisted-pair receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 10base-t module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 manchester encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.3 transmit driver and receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.4 smart squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.8 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9 link test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 automatic link polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.13 memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14 switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15.1 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents
data sheet 5 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx table of contents 3.15.2 address recognition and packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.3 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.4 back off algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.5 inter-packet gap (ipg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.6 illegal frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.7 half duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.8 full duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.9 old broadcast storm filter (0x0b[0]=0 and 0x11[6]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.10 new broadcast/multicast storm (0x0b[0]=1 and 0x11[6]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16 auto tp mdix function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17 port locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.18 vlan setting & tag/untag & port-base vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.19 old fixed ingress bandwidth control (0x0b[0]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20 new scalable egress/ingress bandwidth control (0x0b[0]=1 and 0x33[12]=1) . . . . . . . . . . . . . . . . . 33 3.21 mac table accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 priority setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23 led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.1 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.2 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.3 circuit for single led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23.4 circuit for dual led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.24 mac clone and port5 mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.25 the hardware difference between adm6996lc/lcx/i and adm6996l . . . . . . . . . . . . . . . . . . . . . . 40 4 32 bits mode registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 eeprom registers (0x0b[0]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.1 eeprom register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 serial registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.1 serial register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 packet with priority: normal packet content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 tos ip packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6 eeprom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.7 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5 16 bits mode registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 eeprom basic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 eeprom extended registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3 counter and switch status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.4 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6 hardware, eeprom and smi interface for configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.1 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.2 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3 smi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1 tx/fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.1 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.1.2 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.2 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.3 ac characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3.1 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3.2 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
samurai adm6996lc/lcx/lhx table of contents data sheet 6 rev. 1.31, 2005-12-05 7.3.3 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.3.4 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.3.5 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.3.6 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.3.7 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.3.8 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.3.9 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.3.10 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.3.11 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.3.12 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.3.13 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 8.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
data sheet 7 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of figures figure 1 adm6996lc/lcx/lhx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2 5 tp/fx port + 1 mii port 128 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 3 circuit for single color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4 circuit for dual color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 5 adm6996lc/lcx to cpu with single mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6 mac clone enable and vlan setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7 100m full duplex mac to mac mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8 old router architecture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9 new router architecture using adm6996lc/lcx/lhx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10 cpu generated reset signal requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 11 cpu write eeprom command requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12 serial interface read command timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 13 serial interface reset command timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 14 interconnection between adm6996lc/lcx/lhx, eeprom and cpu . . . . . . . . . . . . . . . . . . . . 159 figure 15 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 16 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 17 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 18 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 19 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 20 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 21 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 22 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 23 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 24 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 25 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 26 reduce mii timing (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 27 reduce mii timing (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 28 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 29 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 30 sdc/sdio timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 31 p-pqfp-128 outside dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 list of figures
data sheet 8 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of tables table 1 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3 io signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6 fixed ingress bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9 pin description(qfp128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 10 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 12 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 14 basic control registers 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 15 reserved register 1 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16 reserved register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18 the max. packet number = 7490 in 100base, 749 in 10base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19 drop scheme for each queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20 vlan mapping table registers 1 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21 reserved register 8 to 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22 note: reference table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26 per port counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27 ethernet packet from layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 28 vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 29 ip packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 30 resetl & eeprom content relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 31 broadcast storming threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32 priority queue weight ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 33 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 34 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 35 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37 basic control registers 1 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 38 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 39 pxso registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 40 vfxl registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 41 vfxh registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 42 tfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 43 pfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 44 tufx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 45 clx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 46 chx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 47 phy_cx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 48 phy_sx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 49 phy_ix_a registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 list of tables
data sheet 9 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx list of tables table 50 phy_ix_b registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 51 anapx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 52 anlpax registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 53 anex registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 54 nptx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 55 lpnpx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 56 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 57 (d) the pin type of eecs, eesk, edi and edo during the operation . . . . . . . . . . . . . . . . . . . 162 table 58 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 59 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 60 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 61 dc electrical characteristics for 3.3 v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 62 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 63 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 64 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 65 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 66 10-base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 67 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 68 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 69 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 70 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 71 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 72 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 73 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 74 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
samurai adm6996lc/lcx/lhx product overview data sheet 10 rev. 1.31, 2005-12-05 1 product overview 1.1 overview the samurai (adm6996lc/lcx/lhx) is a high performance, low cost, highly integrated (controller, phy and memory) five-port 10/100 mbit/s tx/fx plus one 10/100 mac port ethernet switch controller with all ports supporting 10/100 mb/s full/half duplex. the adm6996lc/lcx/lhx is intended for applications for stand alone bridges for low cost soho markets such as wire/adsl/wireless router, ip set top box, vdsl2, gateway and homepna/homeplug applications. the adm6996lcx is the environmentally friendly ?green? package version. the lh solution contains a heat sink which can be used in special circumstances but is not recommended for all projects. adm6996lc/lcx/lhx provides advanced functions such as: 802.1p(q.o.s.), port-based/tag-based vlan, port mac address locking, management, port status, mac address access and bandwidth control . the adm6996lc/lcx/lhx also supports back pressure in half-duplex mode and 802.3x flow control pause packet in full-duplex mode to prevent packet loss when buffer is full. when back pressure is enabled, and there is no receive buffer available for the incoming packet, the adm6996lc/lcx/lhx will issue a jam pattern on the receiving port in half duplex mode and transmit the 802.3x pause packet back to receiving end in full duplex mode. the built-in sram used for packet buffering is divided into 256 bytes/block to achieve the optimized memory utilization through complicated link lists on packets with various lengths. adm6996lc/lcx/lhx also supports priority features by port-base, vlan, ip tos, tcp/udp layer4 destination port number, mac destination address field checking. users can be easily set different priority modes in individual ports, through a small low-cost micro controller to initialize or on-the-fly to configure. each output port supports four queues in the way of fixed n:1 or programmable fairness queuing to fit the bandwidth demand on various types of packets such as voice, video and data. tag/untag, and up to 16 groups of vlan also is supported. an intelligent address recognition algorithm makes adm6996lc/lcx/lhx to recognize up to 2k different mac addresses and enables filtering and forwarding at full wire speed. port mac address locking function is also supported by adm6996lc/lcx/lhx to use on building internet access to prevent multiple users sharing one port traffic. 1.2 features ? supports five 10m/100m auto-detect half/full duplex switch ports with tx/fx interfaces and one mii/gpsi port. ? supports 2k mac addresses table with 4-ways associative hash algorithm. ? supports four queue for qos ? supports priority features by port-based, 802.1p, ip tos of packets, layer4 tcp/udp destination port number and mac address da. ? supports mac dress accessible such as search, add and delete. ? supports engress/ingress 64k scalable bandwidth control. ? supports store & forward architecture and performs forwarding and filtering at non-blocking full wire speed. ? supports buffer allocation with 256 bytes per block ? supports aging function enable/disable. ? supports per port single/dual color mode with power on auto diagnostic. ? supports 802.3x flow control pause packet for full duplex in case buffer is full. ? supports back pressure function for half duplex operation in case buffer is full. ? supports packet length up to 1518/1522 (default)/1536/1784 bytes in maximum. ? broadcast/multicast storm suppression.
data sheet 11 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx product overview ? supports tag-based vlan. up to 16 vlan groups is implemented by the last four bits of vlan id. ? 2bit mac clone to support multiple wan application ? supports tp interface auto mdix function for auto tx/rx swap by strapping-pin. ? easy management 32bits smart counter for per port rx/tx byte/packet count, 16-bit smart counter for per port error count and collision count through serial 32/16 bits mode access. 16 bits mode is mdc/mdio timing compatible. ? supports phy status output for management system. ? 25m crystal only for the whole system. ? 128 qfp package with 0.18um technology. 1.8 v/3.3 v power supply. ? 1.0 w low power consumption. 1.3 applications adm6996lc/lcx/lhx in 128-pin pqfp: ? wire/adsl/wireless/vdsl2 router ? ip setop box, homepna, homeplug application.
samurai adm6996lc/lcx/lhx product overview data sheet 12 rev. 1.31, 2005-12-05 1.4 block diagram figure 1 below shows a simple block diagram of the adm6996lc/lcx/lhx internal blocks. figure 1 adm6996lc/lcx/lhx block diagram po rt 0 po rt 1 po rt 2 ... po rt 4 mlt3 nrz nrzi digital equalizer nrz to 5b 5b to nrz txn7 txp7 driver a/d con v ert er rx n 7 rx p7 base line correction clock generator bias 10/100m mac descrambler data handler jabber detector carrier integrity monitor fifo partition handler scramble r transmit state machine led display control twisted pai r interface led interface ... 10/100m mac 10/100m mac 10/100m mac switching fabric embedded memory mii interface memory bist eeprom handler eeprom interface
data sheet 13 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 2 interface description this chapter describes the interface descriptions for the adm6996lc/lcx/lhx ?pin diagram ? abbreviations ? pin description by function 2.1 pin diagram figure 2 shows the pin diagram for the adm6996lc/lcx/lhx. figure 2 5 tp/fx port + 1 mii port 128 pin diagram dupcol4 gndo vcc3o dupcol3 dupcol2 (bpen) dupcol1 (phyas1) dupcol0 (recanen) vccik gndik rc xi xo vccpll gndpll control vref gndbias rtx vccbias vcca2 txp0 txn0 gnda rxp0 rxn0 vccad gndik (gfcen)txd0 p4fx (p5_busmd0)txd1 (p5_busmd1)txd2 (sdio_md)txd3 ldspd4 gndo vcc3o ldspd3 ldspd2 vccik gndik ldspd1 ldspd0 test vccik gndik gndo vcca2 txp4 txn4 gnda rxp4 rxn4 vccad vc ci k txen (phyas0) txclk/refclk_out rx er gndo gndo vc c3 o rx clk /r efc lk_i n rx dv rx d0 vc ci k gndik cr s col edi (ledmode) eecs eesk (xoven) vc ci k gndik edo cko25m cf g0 gndo vc c3 o spdtnp5 lnkfp5 dp hal fp 5 lnkact4 gndik vc ci k lnkact3 lnkact2 lnkact1 lnkact0 gndo rx d1 rx d2 rx d3 samurai-lc adm6996lc rx n3 rx p3 gnda txn3 txp3 vcca2 nc nc nc nc nc nc vccad rx n2 rx p2 gnda txn2 txp2 vcca2 nc nc nc nc nc nc vccad rx n1 rx p1 gnda txn1 txp1 vcca2 nc nc nc nc nc nc 104 103 105 112 111 110 109 108 107 106 113 114 116 115 117 124 123 122 121 120 119 118 125 126 128 127 68 69 70 71 72 73 74 75 76 77 67 66 65 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 40 41 39 63 64 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 1 31 32 33 34 35 36 37 38
samurai adm6996lc/lcx/lhx interface description data sheet 14 rev. 1.31, 2005-12-05 2.2 abbreviations standard abbreviations for i/o tables: 2.3 pin description by function adm6996lc/lcx/lhx pins are categorized into one of the following groups: ? network media connection ? port 5 mii interface ? led interface ? eeprom interface ? power/ground, 48 pins ? miscellaneous table 1 abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 2 abbreviations for buffer type abbreviations description z high impedance pu pull up, 10 k ? pd pull down, 10 k ? ts tristate capability: the corresponding pin has 3 operational states: low, high and high- impedance. od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics
data sheet 15 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description note: table 1 can be used for reference. table 3 io signals ball no. name pin type buffer type function network media connection 41 rxp_4 ai/o ana receive pair differential data is received on this pin. 37 rxp_3 24 rxp_2 11 rxp_1 126 rxp_0 40 rxn_4 ai/o ana 38 rxn_3 25 rxn_2 12 rxn_1 127 rxn_0 44 txp_4 ai/o ana transmit pair differential data is transmitted on this pin. 34 txp_3 21 txp_2 8 txp_1 123 txp_0 43 txn_4 ai/o ana 35 txn_3 22 txn_2 9txn_1 124 txn_0 port 5 mii interface 63 gfcen i pu, lvttl global flow control enable value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl( rc ) as flow control enable. note: power on setting 0 b flow control capability is depended upon the register setting in corresponding eeprom register 1 b all ports flow control capability is enabled mii_txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in mii mode the bit[0] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. gpsi_txd o 4 ma, pu, lvttl port 5 transmit data in gpsi mode when port 5 is operating in gpsi mode, this pin acts as gpsi transmit data. synchronous to the rising edge of gpsi_txclk. rmii_txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in rmii mode when port 5 is operating in rmii mode, this pin acts as rmii transmit data bit [0]. synchronous to the rising edge of refclk_in.
samurai adm6996lc/lcx/lhx interface description data sheet 16 rev. 1.31, 2005-12-05 61 p5_busmd0 i pd, lvttl port 5 bus mode selection bit 0 value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 5 bus mode selection bit 0. combined with p5_busmd1 , adm6996lc/lcx/lhx provides 3 bus type for port 5. p5_busmd[1:0], interface note: power on setting 00 b mii 01 b gpsi 10 b rmii 11 b reserved and not allowed mii_txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in mii mode the bit[1] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. rmii_txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in rmii mode the bit[1] of rmii transmit data of port 5. synchronous to the rising edge of refclk_in. 60 p5_busmd1 i pd, lvttl port 5 bus mode selection bit 1 value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 5 bus mode selection bit 1. combined with p5_busmd0 , adm6996lc/lcx/lhx provides 3 bus type for port 5. note: power on setting mii_txd2 o 4 ma, pd, lvttl port 5 transmit data bit 2 in mii mode the bit[2] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. 59 sdio_md i pd, lvttl sdc/sdio mode selection value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl for sdio 32/16 bits selection. 0 b 32 bits mode 1 b 16 bits mode. same timing as mdc/mdio. mii_txd3 o 4 ma, pd, lvttl port 5 transmit data bit 3 in mii mode the bit[3] of mii transmit data of port 5. synchronous to the rising edge of mii_txclk. table 3 io signals (cont?d) ball no. name pin type buffer type function
data sheet 17 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 66 phyas0 i pd, lvttl phy address msb bit 0 during power on reset, value will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as phy start address select. phyas[1:0] = 00 b and phy address starts from 01000 b . note: power on setting mii_txen o 8 ma, pd, lvttl port 5 transmit enable txen in mii mode active high to indicate that the data on mii_txd[3:0] is valid. synchronous to the rising edge of mii_txclk. gpsi_txen o 8 ma, pd, lvttl port 5 transmit enable txen in gpsi mode active high to indicate that the data on gpsi_txd is valid. synchronous to the rising edge of gpsi_txclk. rmii_txen o 8 ma, pd, lvttl port 5 r transmit enable txen in rmii mode active high to indicate that the data on rmii_txd[1:0] is valid. synchronous to the rising edge of refclk_in. 74 mii_rxd0 i pd, lvttl port 5 receive data bit 0 in mii mode the bit[0] of mii receive data, synchronous to the rising edge of mii_rxclk. gpsi_rxd i pd, lvttl port 5 receive data in gpsi mode in gpsi mode, this acts as receive data input, synchronous to the rising edge of gpsi_rxclk. rmii_rxd0 i pd, lvttl port 5 receive data bit 0 in rmii mode the bit[0] of rmii receive data, synchronous to the rising edge of refclk_in. 100 mii_rxd1 i pd, lvttl port 5 receive data bit 1in mii mode the bit[1] of mii receive data, synchronous to the rising edge of mii_rxclk. rmii_rxd1 i pd, lvttl port 5 receive data bit 1in rmii mode bit[1] of rmii receive data, synchronous to the rising edge of refclk_in. 101 mii_rxd2 i pd, lvttl port 5 receive data bit 2 in mii mode the bit[2] of mii receive data. synchronous to the rising edge of mii_rxclk. 102 mii_rxd3 i pd, lvttl port 5 receive data bit 3 in mii mode the bit[3] of mii receive data. synchronous to the rising edge of mii_rxclk. 73 mii_rxdv i pd, lvttl port 5 receive data valid in mii mode active high to indicate that the data on mii_rxd[3:0] is valid. synchronous to the rising edge of mii_rxclk. rmii_crsdv i pd, lvttl port 5 carrier sense and receive data valid in rmii mode active high to indicate that the data on rmii_rxd[1:0] is valid. synchronous to the rising edge of refclk _in. table 3 io signals (cont?d) ball no. name pin type buffer type function
samurai adm6996lc/lcx/lhx interface description data sheet 18 rev. 1.31, 2005-12-05 68 mii_rxer i pd, lvttl port 5 receive error in mii mode active high to indicate that there is error on the mii_rxd [3:0]. upon receiving this signal, adm6996lc/lcx/lhx will send error symbol onto the medium. only valid in 100m operation. rmii_rxer i pd, lvttl port 5 receive error in rmii mode active high to indicate that there is error on the rmii_ rxd[1:0]. upon receiving this signal, adm6996lc/lcx/lhx will send error symbol onto the medium. only valid in 100m operation. 77 mii_crs i pd, lvttl port 5 carrier sense in mii mode in full duplex mode, mii_p5crs reflects the receive carrier sense situation on medium only; in half duplex, mii_crs will be high both in receive and transmit condition. gpsi_crs i pd, lvttl port 5 carrier sense in gpsi mode in full duplex mode, gpsi_crs reflects the receive carrier sense situation on medium only; in half duplex, gpsi_crs will be high both in receive and transmit condition. 78 mii_col i pd, lvttl port 5 collision input in mii mode active high to indicate that there is collision on the medium. stay low in full duplex operation. gpsi_col i pd, lvttl port 5 collision input in gpsi mode active high to indicate that there is collision on the medium. stay low in full duplex operation. 72 mii_rxclk i pd, lvttl port 5 receive clock inputin mii mode mii_rxdv and mii_rxd[3:0] are synchronous to the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_ rxclk i pd, lvttl port 5 receive clock input in gpsi mode gpsi_rxd are synchronous to the rising edge of this clock. it is non-continuous 10 mhz clock input. refclk_in i pd, lvttl 50mhz reference clock input in rmii mode rmii_rxd[1:0], rmii_txd[1:0], rmii_txen and rmii_crsdv are synchronous to the rising edge of this clock. 67 mii_txclk i pd, lvttl port 5 transmit clock input in mii mode mii_txen and mii_txd[3:0] are output at the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_txclk i pd, lvttl port 5 transmit clock input in gpsi mode gpsi_txen and gpsi_txd are synchronous to the rising edge of this clock. it is continuous 10 mhz clock input. refclk _ out o 8 ma, pd, lvttl 50mhz reference clock output in rmii mode this pin is used as 50 mhz reference clock signal output pin when port 5 operates in rmii mode. table 3 io signals (cont?d) ball no. name pin type buffer type function
data sheet 19 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 89 spdtnp5 i pd, lvttl port 5 speed input 0 b 100m 1 b 10m 90 lnkfp5 i pd, lvttl port 5 link fail status input 0 b link up 1 b link failed 91 dphalfp5 i pd, lvttl port 5 duplex status input 0 b full duplex 1 b half duplex led interface 103 dupcol4 o 8 ma, pd, lvttl port 4 duplex /collision led in full duplex mode, this pin acts as duplex led for port 4, respectively; in half duplex mode, it is collision led for each port. see chapter 3.23 led display for more detail. 106 dupcol3 o 8 ma, pd, lvttl port 3 duplex /collision led in full duplex mode, this pin acts as duplex led for port 3, respectively; in half duplex mode, it is collision led for each port. see chapter 3.23 led display for more detail. 107 bpen i pu, lvttl recommend back-pressure in half-duplex the value on this pin will be latched by adm6996lc/lcx/lhx during power on reset as the beck- pressure enable in half-duplex mode. note: power on setting 0 b disable back-pressure 1 b enable back-pressure dupcol2 o 8 ma, pu, lvttl port 2 duplex-collision led in full duplex mode, this pin acts as port 2 duplex led; in half duplex mode, it is collision led for port 2. see chapter 3.23 led display for more detail. 108 phyas1 i pd, lvttl recommend phy address bit 1 value on this pin will be latched by adm6996lc/lcx/lhx during power on reset as the phy address recommend value bit 1. see phyas0 description for more detail. note: power on setting dupcol1 o 8 ma, pd, lvttl port 1 duplex-collision led in full duplex mode, this pin acts as port 1 duplex led; in half duplex mode, it is collision led for port 1. see chapter 3.23 led display for more detail. table 3 io signals (cont?d) ball no. name pin type buffer type function
samurai adm6996lc/lcx/lhx interface description data sheet 20 rev. 1.31, 2005-12-05 109 recanen i pu, lvttl recommend auto negotiation enable only valid for twisted pair interface. programming this bit to 1 has no effect on the fiber port. note: power on setting. 0 b disable all tp port auto negotiation capability 1 b enable all tp port auto negotiation capability dupcol0 o 8 ma, pu, lvttl port 0 duplex-collision led in full duplex mode, this pin acts as port 0 duplex led; in half duplex mode, it is the collision led for port 0. see chapter 3.23 led display for more detail. 92 lnkact_4 o 8 ma, pd, lvttl link/activity led of port 4 to 0 used to indicate corresponding port? s link/activity status, see chapter 3.23 led display for more detail. 95 lnkact_3 96 lnkact_2 97 lnkact_1 98 lnkact_0 58 ldspd_4 o 8 ma, pd, lvttl port 4 to port 0 speed led used to indicate corresponding port? s speed status, see chapter 3.23 led display for more detail. 55 ldspd_3 54 ldspd_2 51 ldspd_1 50 ldspd_0 eeprom interface 84 edo i pu, lvttl eeprom data output this pin is used to input eeprom data when reading eeprom. during adm6996lc/lcx/lhx initialization, adm6996lc/lcx/lhx will drive eeprom interface signal to read settings from eeprom. any other devices attach to eeprom interface should driv e hi-z or keep tristate during this period. see chapter 4.6 eeprom access for more detail. 80 ifsel i pd, lvttl interface selection after adm6996lc/lcx/lhx initialization, this pin is used to select using eeprom interface or sdc/sdio interface. eecs/ifsel interface 0 b sdc/sdio interface 1 b eeprom interface eecs o 4 ma, pd, lvttl eeprom chip select during adm6996lc/lcx/lhx initialization, this pin is used as the eeprom chip select signal. during adm6996lc/lcx/lhx initialization, adm6996lc/lcx/lhx will drive eeprom interface signal to read settings from the eeprom. any other devices attached to the eeprom interface should drive hi-z or keep tristate during this period. see chapter 4.6 eeprom access for more detail. table 3 io signals (cont?d) ball no. name pin type buffer type function
data sheet 21 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 81 xoven i pd, lvttl cross over enable value on this pin (active low) will be latched by adm6996lc/lcx/lhx at the rising edge of resetl for port 4~0 crossover auto detect (only available in tp interface). note: power on setting. 0 b disable 1 b enable eesk i/o 4 ma, pd, lvttl eeprom serial clock during adm6996lc/lcx/lhx initialization, this pin is used to output clock to eeprom. after adm6996lc/lcx/lhx initialization process is done, this pin is used as eeprom interface clock input if ifsel = 1. sdc i pd, lvttl serial management interface clock input if ifsel = 0, this pin is used as a serial management interface clock input. 79 led_mode i pd, lvttl enable mac to choose led display mode value on this pin will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as dsingle/dual color led mode control signal. see chapter 3.23 led display for more detail. note: power on setting. edi i/o 8 ma, pd, lvttl eeprom serial data input during adm6996lc/lcx/lhx initialization, this pin is used to output address and command to access eeprom. after the initialization process is done, this pin becomes an input pin to monitor eeprom data if ifsel = 1. sdio i/o 8 ma, pd, lvttl serial management interface data input/output if ifsel = 0, this pin is used as data input/output pin of serial management interface. power/ground, 48 pins 10, 23, 36, 42, 125 gnda gnd ? ground used by ad block 7, 20, 33, 45, 122 vcca2 pwr ? 1.8 v, power used by tx line driver 13, 26, 39, 128 vccad pwr ? 3.3 v, power used by ad block 119 gndbias gnd ? ground used by bias block 121 vccbias pwr ? 3.3 v, power used by bias block. 116 gndpll gnd ? ground used by pll table 3 io signals (cont?d) ball no. name pin type buffer type function
samurai adm6996lc/lcx/lhx interface description data sheet 22 rev. 1.31, 2005-12-05 115 vccpll pwr ? 1.8 v, power used by pll 47, 52, 64, 76, 83, 93 gndik gnd ? ground used by digital core 48, 53, 75, 82, 94, 110 vccik pwr ? 1.8 v, power used by digital core 46, 57, 70, 87, 99, 104 gndo gnd ? ground used by digital pad 56, 71, 88, 105 vcc3o pwr ? 3.3 v, power used by digital pad miscellaneous 62 p4fx i pd, lvttl port 4 fiber selection during power on reset, value will be latched by adm6996lc/lcx/lhx at the rising edge of resetl as port 4 fiber select. 0 b twisted pair mode 1 b fiber mode 65 int_n o od,8 ma interrupt active low interrupt signal to indicate the status change in the interrupt status register. interrupt signal will keep active low until host read the status of isr register. 0 b interrupt 1 b not interrupt 69 wait_init i pd, lvttl wait initialization this pin will be used to pause all activities after power up until eeprom is loaded successfully or cpu initialization is done. 0 b pause until loading eeprom is done. 1 b pause until eeprom successfully loaded or cpu initialization is done. 1, 2, 3, 4, 5, 6, 14, 15, 16, 17, 18, 19, 27, 28, 29, 30, 31, 32 nc - - not connected 49 test i pd, lvttl test mode reserved and should be kept 0 when under normal operation. 86 cfg0 i pu, lvttl configuration 0 reserved and should be kept 0 when under normal operation. 85 cko25m o 8 ma, pd, lvttl 25mhz clock output free running 25 mhz clock output (even during power on reset) table 3 io signals (cont?d) ball no. name pin type buffer type function
data sheet 23 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx interface description 112 rc i st rc input for power on reset this pin is sampled by using the 25 mhz free running clock signal which inputs from xi to generate the low-active reset signal, resetl. see chapter 7.3.2 power on reset for the timing requirement. 113 xi ai ana 25mhz crystal /oscillator input 25mhz crystal or oscillator input. variation is limited to +/- 50ppm. 114 xo ao ana 25m crystal output when connected to oscillator, this pin should be left unconnected. 120 rtx ai ana constant voltage reference external 1.0 k ? 1% resistor connection to ground. 118 vref ai ana analog reference voltage used by internal bias circuit for voltage reference. external 0.1uf capacitor connection to ground for noise filter. 117 control ai/o ana fet control signal the pin is used to control fet for 3.3 v to 1.8 v regulator. external 0.1uf capacitor connection to ground for noise filter, even the pin is un-connected. table 3 io signals (cont?d) ball no. name pin type buffer type function
samurai adm6996lc/lcx/lhx function description data sheet 24 rev. 1.31, 2005-12-05 3 function description 3.1 functional descriptions the adm6996lc/lcx/lhx integrates five 100base-x physical sub-layer (phy), 100base-tx physical medium dependent (pmd) transceivers, five complete 10base-t modules, a 6 port 10/100 switch controller and one 10/100 mii/gpsi mac and memory into a single chip for both 10mbit/s, 100mbit/s ethernet switch operation. it also supports 100base-fx operation through external fiber-optic transceivers. the device is capable of operating in either full duplex mode or half-duplex mode in 10mbit/s and 100mbit/s. operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic. the adm6996lc/lcx/lhx consists of three major blocks: ? 10/100m phy block ? switch controller block ?built-in ssram the interfaces used for communication between the phy block and switch core is an mii interface. an auto mdix function is supported in this block. this function can be enabled and disabled by the hardware pin. 3.2 10/100m phy block the 100base-x section of the device implements the following functional blocks: ? 100base-x physical coding sub-layer (pcs) ? 100base-x physical medium attachment (pma) ? twisted-pair transceiver (pmd) the 100base-x and 10base-t sections share the following functional blocks: ? clock synthesizer module ? mii registers ? ieee 802.3u auto negotiation 3.3 100base-x module the adm6996lc/lcx/lhx implements a 100base-x compliant pcs and pma and 100base-tx compliant tp- pmd as illustrated in figure 2. bypass options for each of the major functional blocks within the 100base-x pcs provides flexibility for various applications. 100mbit/s phy loop back is included for diagnostic purpose. 3.4 100base-x receiver the 100base-x receiver consists of functional blocks required to recover and condition the 125mbit/s receive data stream. the adm6996lc/lcx/lhx implements the 100base-x receiving state machine diagram as given in the ansi/ieee standard 802.3u, clause 24. the 125mbit/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100base-tx application. alternatively, the receive data stream may be generated by an external optical receiver as in a 100base-fx application. the receiver block consists of the following functional sub-blocks: ? a/d converter ? adaptive equalizer and timing recovery module ? nrzi/nrz and serial/parallel decoder ?de-scrambler ? symbol alignment block ? symbol decoder
data sheet 25 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description ? collision detect block ? carrier sense block ? stream decoder block 3.4.1 a/d converter a high performance a/d converter with a 125 mhz sampling rate converts signals received on the rxp/rxn pins to 6 bits data streams. it possess an auto-gain-control capability that will further improve receive performance especially under long cabling or harsh detrimental signal integrity. due to high pass characteristic on a transformer, a built in base-line-wander correcting circuit will be cancelled out and its dc level restored. 3.4.2 adaptive equalizer and timing recovery module all digital design is especially immune to noise environments and achieves better correlation between production and system testing. baud rate adaptive equalizer/timing recovery compensates for line loss induced from twisted pairs and tracks a far end clock at 125m samples per second. adaptive equalizer?s implemented with feed forward and decision feedback techniques meet the requirement of ber with less than 10-12 for transmission on a cat5 twisted pair cable ranging from 0 to 120 meters. 3.4.3 nrzi/nrz and serial/parallel decoder the recovered data is converted from nrzi to nrz. the data is not necessarily aligned to the 4b/5b code group?s boundary. 3.4.4 data de-scrambling the de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xored by the deciphering lfsr and de-scrambled. in order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the de-scrambler the hold timer starts a 722 micro second countdown. upon detection of sufficient idle symbols within the 722 micro sec. period, the hold timer will reset and begin a new countdown. this monitoring operation will continue indefinitely given an operating network connection operating with good signal integrity. if the link state monitor does not recognize sufficient unscrambled idle symbols within the 722 micro second period, the de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. 3.4.5 symbol alignment the symbol alignment circuit in the adm6996lc/lcx/lhx determines code word alignment by recognizing the /j/k delimiter pair. this circuit operates on unaligned data from the de-scrambler. once the /j/k symbol pair (11000 10001 b ) is detected, subsequent data is aligned on a fixed boundary. 3.4.6 symbol decoding the symbol decoder functions is a look-up table that translates incoming 5b symbols into 4b nibbles as shown in table 1. the symbol decoder first detects the /j/k symbol pair preceded by idle symbols and replaces the symbol with a mac preamble. all subsequent 5b symbols are converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r symbol pair denoting the end of stream delimiter (esd). the translated data is presented on the internal rxd[3:0] signal lines where rxd[0] represents the least significant bit of the translated nibble.
samurai adm6996lc/lcx/lhx function description data sheet 26 rev. 1.31, 2005-12-05 3.4.7 valid data signal the valid data signal (rxdv) indicates that recovered and decoded nibbles are being presented on the internal rxd[3:0] synchronous receive clock, rxclk. rxdv is asserted when the first nibble of a translated /j/k is ready for transfer over the internal mii. it remains active until either the /t/r delimiter is recognized, link test indicates failure, or no signal is detected. on any of these conditions, rxdv is de-asserted. 3.4.8 receive errors the rxer signal is used to communicate receiver error conditions. while the receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not map to a valid code-group. 3.4.9 100base-x link monitor the 100base-x link monitor function allows the receiver to ensure that reliable data is being received. without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. the adm6996lc/lcx/lhx performs the link integrity test as outlined in ieee 100base-x (clause 24) link monitor state diagram. the link status is multiplexed with 10mbit/s link status to form the reportable link status bit in the serial management register 1h, and driven to the lnkact pin. when persistent signal energy is detected on the network, the logic moves into a link-ready state after approximately 500 micro secs, and waits for an enable from the auto negotiation module. when received, the link- up state is entered, and the transmission and reception logic blocks become active. should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. 3.4.10 carrier sense carrier sense (crs) for 100mbit/s operation is asserted upon the detection of two non contiguous zeros occurring within any 10-bit boundary of the received data stream. the carrier sense function is independent of symbol alignment. in switch mode, crs is asserted during either packet transmission or reception. for repeater mode, crs is asserted only during packet reception. when the idle symbol pair is detected in the received data stream, crs is de-asserted. in repeater mode, crs is only asserted due to receive activity. crs is intended to encapsulate rxdv. 3.4.11 bad ssd detection a bad start of stream delimiter (bad ssd) is an error condition that occurs in the 100base-x receiver if a carrier is detected (crs asserted) and a valid /j/k set of code-group (ssd) is not received. if this condition is detected, then the adm6996lc/lcx/lhx will assert rxer and present rxd[3:0] = 1110 b to the internal mii for the cycles that correspond to received 5b code-groups until at least two idle code-groups are detected. once at least two idle code groups are detected, rxer and crs become de-asserted. 3.4.12 far-end fault auto negotiation provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred for 100base-tx. as auto negotiation is not currently specified for operation over fiber, the far end fault indication function (fefi) provides this capability for 100base-fx applications. a remote fault is an error in the link that one station can detect while the other cannot. an example of this is a disconnected wire at a station?s transmitter. this station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. a 100base-fx station that detects such a remote fault may modify its transmitted idle stream from all 1 b ?s to a group of 84 1 b ?s followed by a single 0 b . this is referred to as the fefi idle pattern.
data sheet 27 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.5 100base-tx transceiver the adm6996lc/lcx/lhx implements a tp-pmd compliant transceiver for 100base-tx operation. the differential transmit driver is shared by the 10base-t and 100base-tx subsystems. this arrangement results in one device that uses the same external magnetic for both the 10base-t and the 100base-tx transmissions with a simple rc component connection. the individually wave-shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmission output driver selection. 3.5.1 transmit drivers the adm6996lc/lcx/lhx 100base-tx transmission driver implements mlt-3 translation and wave-shaping functions. the rise/fall time of the output signal is closely controlled to conform to the target range as specified in the ansi tp-pmd standard. 3.5.2 twisted-pair receiver for 100base-tx operation, the incoming signal is detected by the on-chip twisted-pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits. the adm6996lc/lcx/lhx uses an adaptive equalizer that changes filter frequency response in accordance with cable length. the cable length is estimated based on the incoming signal strength. the equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. 3.6 10base-t module the 10base-t transceiver module is ieee 802.3 compliant. it includes the receiver, transmitter, collision, heartbeat, loop back, jabber, wave shaper, and link integrity functions, as defined in the standard. figure 3 provides an overview for the 10base-t module. the adm6996lc/lcx/lhx 10base-t module is comprised of the following functional blocks: ? manchester encoder and decoder ? collision detector ? link test function ? transmit driver and receiver ? serial and parallel interface ? jabber and sqe test functions ? polarity detection and correction 3.6.1 operation modes the adm6996lc/lcx/lhx 10base-t module is capable of operating in either half-duplex mode or full-duplex mode. in half-duplex mode, the adm6996lc/lcx/lhx functions as an ieee 802.3 compliant transceiver with fully integrated filtering. the col signal is asserted during collisions or jabber events, and the crs signal is asserted during transmit and receive. in full duplex mode the adm6996lc/lcx/lhx can simultaneously transmit and receive data. 3.6.2 manchester encoder/decoder data encoding and transmission begins when the transmission enable input (txen) goes high and continues as long as the transceiver is in a good link state. transmission ends when the transmission enable input goes low. the last transition occurs at the center of the bit cell if the last bit is a 1 b , or at the boundary of the bit cell if the last bit is 0 b . decoding is accomplished using a differential input receiver circuit and a phase-locked loop that separate the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when
samurai adm6996lc/lcx/lhx function description data sheet 28 rev. 1.31, 2005-12-05 no more mid bit transitions are detected. within one and a half bit times after the last bit, carrier sense is de- asserted. 3.6.3 transmit driver and receiver the adm6996lc/lcx/lhx integrates all the required signal conditioning functions in its 10base-t block such that external filters are not required. only one isolation transformer and impedance matching resistors are needed for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly. 3.6.4 smart squelch the smart squelch circuit is responsible for determining when valid data is present on the differential receive. the adm6996lc/lcx/lhx implements an intelligent receive squelch on the rxp/rxn differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10base-t standard) to determine the validity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150ns. finally, the signal must exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected. only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating the end of a packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-of-packet detection. the receive squelch threshold level can be lowered for use in longer cable applications. this is achieved by setting bit 10 of register address 11 h . 3.7 carrier sense carrier sense (crs) is asserted due to receive activity once valid data is detected via the smart squelch function. for 10 mbit/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 mbit/s full duplex and repeater mode operations, the crs is asserted only due to receive activity. 3.8 jabber function the jabber function monitors the adm6996lc/lcx/lhx output and disables the transmitter if it attempts to transmit a longer than legal sized packet. if txen is high for greater than 24ms, the 10base-t transmitter will be disabled. once disabled by the jabber function, the transmitter stays disabled for the entire time that the txen signal is asserted. this signal has to be de-asserted for approximately 256 ms (the un-jab time) before the jabber function re-enables the transmit outputs. the jabber function can be disabled by programming bit 4 of register address 10 h to high. 3.9 link test function a link pulse is used to check he integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted-pair transmitter, receiver, and collision detection functions. the link pulse generator produces pulses as defined in ieee 802.3 10base-t standard. each link pulse is nominally 100ns in duration and is transmitted every 16 ms, in the absence of transmit data.
data sheet 29 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.10 automatic link polarity detection the adm6996lc/lcx/lhx?s 10base-t transceiver module incorporates an ?automatic link polarity detection circuit?. the inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. if the input polarity is reversed, the error condition will be automatically corrected and reported in bit 5 of register 10 h . 3.11 clock synthesizer the adm6996lc/lcx/lhx implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. the clock source must be a ttl level signal at 25 mhz +/- 50ppm 3.12 auto negotiation the auto negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. for further detail regarding auto negotiation, refer to clause 28 of the ieee 802.3u specification. the adm6996lc/lcx/lhx supports four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. highest priority is relative to the following list: ? 100base-tx full duplex (highest priority) ? 100base-tx half duplex ? 10base-t full duplex ? 10base-t half duplex (lowest priority) 3.13 memory block the adm6996lc/lcx/lhx?s built in memory is divided into two blocks. one is a mac addressing table and the other one is a data buffer. the mac address learning table size is 2k entries with each entry occupying eight bytes length. these eight bytes of data include a 6 byte source address, vlan information, port information and an aging counter. a data buffer is divided into 256 bytes/block. the adm6996lc/lcx/lhx buffer management is per port fixed block number and all ports share one global buffer. this architecture can get better memory utilization and network balance at different speeds and duplex test conditions. received packets will separate into several 256 bytes/block and chain together. if a packet size is more than 256 bytes then the adm6996lc/lcx/lhx will chain two or more blocks to store receiving packets. 3.14 switch functional description the adm6996lc/lcx/lhx uses a ?store & forward? switching approach for the following reason: ? store & forward switches allow switching between different speed media (e.g. 10basex and 100basex). such switches require large elastic buffers especially when bridging between a server on a 100 mbit/s network and clients on a 10 mbit/s segment. ? store & forward switches improve overall network performance by acting as a ?network cache? ? store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (fcs) before forwarding to the destination port. 3.15 basic operation the adm6996lc/lcx/lhx receives incoming packets from one of its ports, searches in the address table for the destination mac address and then forwards the packet to the other port within the same vlan group, where
samurai adm6996lc/lcx/lhx function description data sheet 30 rev. 1.31, 2005-12-05 appropriate. if the destination address is not found in the address table, the adm6996lc/lcx/lhx treats the packet as a broadcast packet and forwards the packet to the other ports within the same vlan group. the adm6996lc/lcx/lhx automatically learns the port number of attached network devices by examining the source mac address of all incoming packets at wire speed. if the source address is not found in the address table, the device adds it to the table. 3.15.1 address learning a four-way hash algorithm is implemented to allow the maximum of 4 different addresses with the same hash key to be stored at the same time. up to 2k entries can be created and all entries are stored in the internal ssram. an address is stored in the address table. the adm6996lc/lcx/lhx searches for the source address (sa) of an incoming packet in the address table and acts as below: 1. if the sa was not found in the address table (a new address), the adm6996lc/lcx/lhx waits until the end of the packet (non-error packet) and updates the address table. if the sa was found in the address table, then the aging value of each corresponding entry will be reset to 0 b . 2. when the da is pause command, then the learning process will be disabled automatically by adm6996lc/lcx/lhx. 3.15.2 address recognition and packet forwarding the adm6996lc/lcx/lhx forwards the incoming packets between bridged ports according to the destination address (da) as below. all the packet forwarded will check the vlan first. a forwarding port must be the within the same vlan as the source port. if the da is a unicast address and the address was found in the address table, the adm6996lc/lcx/lhx will check the port number and act as follows: ? if the port number is equal to the port on which the packet was received, the packet is discarded. ? if the port number is different, the packet is forwarded across the bridge. ? if the da is a unicast address and the address was not found, the adm6996lc/lcx/lhx treats it as a multicast packet and forwards it across the bridge. ? if the da is a multicast address, the packet is forwarded across the bridge. ? if the da is a pause command (01 80 c2 00 00 01 h ), then this packet will be dropped by the adm6996lc/lcx/lhx. the adm6996lc/lcx/lhx can issue and learn pause commands. ? the adm6996lc/lcx/lhx will forward the packet with a da of (01 80 c2 00 00 00 h ), filter out the packet with a da of (01 80 c2 00 00 01 h ), and forward a packet with a da of (01-80-c2-00-00-02 h to 01 80 c2 00 00 0f h ) 3.15.3 address aging address aging is supported for topology changes such as an address moving from one port to another. when this happens, the adm6996lc/lcx/lhx internally has a 300 second timer which will ?age-out? (remove) the address from the address table. the aging function can be enabled/disabled by the user. normally, disabling an aging function is for security purposes. 3.15.4 back off algorithm the adm6996lc/lcx/lhx implements the truncated exponential back off algorithm compliant to the 802.3 csma-cd standard. the adm6996lc/lcx/lhx will restart the back off algorithm by choosing 0-9 collision counts. the adm6996lc/lcx/lhx resets the collision counter after 16 consecutive retransmit trials. 3.15.5 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the typical number is 96 bits at a time. the value is 9.6 micro secs for 10 mbit/s ethernet, 960ns for 100 mbit/s fast ethernet and 96ns for 1000m.
data sheet 31 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description the adm6996lc/lcx/lhx provides an option of 92 bit gap in an eeprom to prevent packet loss when flow control is turned off and clock p.p.m. values differ. 3.15.6 illegal frames the adm6996lc/lcx/lhx will discard all illegal frames such as runt packets (less than 64 bytes), oversized packets (greater than 1518 or 1522 bytes) and bad crc. dribbling packing with good crc value will be accepted by the adm6996lc/lcx/lhx. in case of bypass mode enable, the adm6996lc/lcx/lhx will support tag and untagged packets with sizes up to 1522 bytes. in case of non-bypass mode, the adm6996lc/lcx/lhx will support tag packets up to 1526bytes and untagged packets up to 1522bytes. 3.15.7 half duplex flow control a back pressure function is supported for half-duplex operations. when the adm6996lc/lcx/lhx cannot allocate a receive buffer for an incoming packet (buffer full), the device will transmit a jam pattern on the port, thus forcing a collision. back pressure is enabled by the bpen set during reset assertion. an infineon proprietary algorithm is implemented inside the adm6996lc/lcx/lhx to prevent the back pressure function causing hub partitioned under heavy traffic environment and reducing the packet loss rate to increase the whole system performance. 3.15.8 full duplex flow control when full duplex port run out of its receive buffer, a pause packet command will be issued by adm6996lc/lcx/lhx to notice the packet sender to pause transmission. this frame based flow control is totally compliant to ieee 802.3x. adm6996lc/lcx/lhx can issue or receive pause packet. 3.15.9 old broadcast storm filter (0x0b[0]=0 and 0x11[6]=0) if the broadcast storm filter is enabled, the broadcast packets over 50 ms of the threshold will be discarded by the threshold setting. see eeprom reg.10 h . broadcast storm mode: time interval: 50ms max. packet number = 7490 in 100base, 749 in 10base 3.15.10 new broadcast/multicast storm (0x0b[0]=1 and 0x11[6]=1) adm6996lc/lcx allows users to limit the traffic of the broadcast address (da = ffffffffffff h ) to prevent them from blocking the switch bandwidth. if users also want to limit the multicast packets(da[40] = 1 b ), they can table 4 the max. packet number = 7490 in 100base, 749 in 10base per port falling threshold 00 b 01 b 10 b 11 b all 100tx disable 7440fps 14880fps 29760fps not all 100tx disable 744fps 1488fps 2976fps table 5 the max. packet number = 7490 in 100base, 749 in 10base per port rising threshold 00 b 01 b 10 b 11 b all 100tx disable 14880fps 29760fps 59520fps not all 100tx disable 1488fps 2976fps 5952fps
samurai adm6996lc/lcx/lhx function description data sheet 32 rev. 1.31, 2005-12-05 set the multicast packet counted into storming counter (see 0010 h [5]) function. two thresholds and storm enable bits (see 003b h and 003c h ) are used to control the broadcast storm. 1. time scale. adm6996lc/lcx uses 50ms as a scale to meter the storm packets. 2. storm keeps on at least 1.6 seconds if any of the ports meets the rising threshold in the 4 consecutive 50 ms intervals. in these 1.6 seconds, the ports meeting the rising threshold will start to discard the broadcast or multicast packets until the 50 ms interval expires. users could also disable input filter (see 000b h [14]) function to forward above packets to the un-congested port instead of discarding directly. 3. storm finishes. after the 1.6-second storm period, adm6996lc/lcx will check the port that makes the storm on. if all of these ports meet the falling threshold in the 2 consecutive 50 ms intervals and no other ports satisfy the rising threshold at the same time, the storm will finish. 3.16 auto tp mdix function at normal application which switch connect to nic card is by one by one tp cable. if switch connect other device such as another switch must by two way. first one is cross over tp cable. second way is use extra rj45 which crossover internal tx+- and rx+- signal. by second way customer can use one by one cable to connect two switch devices. all these effort need extra cost and not good solution. adm6996lc/lcx/lhx provide auto mdix function which can adjust tx+- and rx+- at correct pin. user can use one by one cable between adm6996lc/lcx/lhx and other device. this function can be enable/disable by hardware pin and eeprom configuration register 01 h ~ 09 h bit 15. if hardware pin set all port at auto mdix mode then eeprom setting is useless. if hardware pin set all port at non auto mdix mode then eeprom can set each port this function enable or disable. 3.17 port locking port locking function will provide customer simple way to limit per port user number to one. if this function is turn on then adm6996lc/lcx/lhx will lock first mac address in learning table. after this mac address locking will never age out except reset signal. another mac address which not same as locking one will be dropped. adm6996lc/lcx/lhx provide one mac address per port. this function is per port setting. when turn on port locking function, recommend customer turn off aging function. see eeprom register 12 h bit 0~8. 3.18 vlan setting & tag/untag & port-base vlan adm6996lc/lcx/lhx supports bypass mode and untagged port as default setting while the chip is power-on. thus, every packet with or without tag will be forwarded to the destination port without any modification by adm6996lc/lcx/lhx. meanwhile port-base vlan could be enabled according to the pvid value (user define 4bits to map 16 groups written at register 13 h to register 22 h ) of the configuration content of each port. adm6996lc/lcx/lhx also supports 16 802.1q vlan groups. in vlan four bytes tag include twelve vlan id. adm6996lc/lcx/lhx learn user define four bits of vid. if user need to use this function, two eeprom registers are needed to be programmed first: * port vid number at eeprom register 01 h ~ 09 h bit 13~10, register 28 h ~ 2b h and register 2c h bit 7~0: adm6996lc/lcx/lhx will check coming packet. if coming packet is non vlan packet then adm6996lc/lcx/lhx will use pvid as vlan group reference. adm6996lc/lcx/lhx will use packet?s vlan value when receive tagged packet. * vlan group mapping register. eeprom register 13 h ~ 22 h define vlan grouping value. user use these register to define vlan group. parameter rising threshold falling threshold all link ports are 100m 100m threshold (see 003b h [12:0]) 1/2 100m threshold all link ports are not all 100m 10m threshold (see 003c h [12:0]) 1/2 10m threshold
data sheet 33 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description user can define each port as tag port or untag port by configuration register bit 4. the operation of packet between tag port and untag port can explain by follow example: example1: port receives untag packet and send to untag port. adm6996lc/lcx/lhx will check the port user define four bits of vlan id first then check vlan group resister. if destination port same vlan as receiving port then this packet will forward to destination port without any change. if destination port not same vlan as receiving port then this packet will be dropped. example2: port receives untag packet and send to tag port. adm6996lc/lcx/lhx will check the port user define fours bits of vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port with four byte vlan tag and new crc. if destination port not same vlan as receiving port then this packet will be dropped. example3: port receives tag packet and send to untag port. adm6996lc/lcx/lhx will check the packet vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port after remove four bytes with new crc error. if destination port not same vlan as receiving port then this packet will be dropped. example4: port receives tag packet and send to tag port. adm6996lc/lcx/lhx will check the user define packet vlan id first then check vlan group resister. if destination port same vlan as receiving port than this packet will forward to destination port without any change. if destination port not same vlan as receiving port then this packet will be dropped. 3.19 old fixed ingress bandwidth control (0x0b[0]=0) adm6996lc/lcx/lhx also supports adm6996l compatible bandwidth control with fixed rate. 3.20 new scalable egress/ingress bandwidth control (0x0b[0]=1 and 0x33[12]=1) bandwidth control function is useful on community networks for different levels of service. adm6996lc/lcx/lhx provides scalable egress/ingress bandwidth control. users can set any value that is based on a 64k unit. 3.21 mac table accessible cpu accesses switch internal mac table is provided by adm6996lc/lcx/lhx. cpu can search, add, delete and set adm6996lc/lcx/lhx internal mac table through a serial interface. search: cpu can search target mac address switch port number. add: cpu can add mac address to learning table. delete: cpu can delete mac address from learning table. set mac address: cpu can set mac address as static or no static address. static means not aging out. 3.22 priority setting it is a trend that data, voice and video will be put on networking, switch not only deal data packet but also provide service of multimedia data. adm6996lc/lcx/lhx provides two priority queues on each port with n:1 rate. see eeprom reg.10 h . this priority function can set three ways as below: * by port base: set specific port at specific queue. adm6996lc/lcx/lhx only check the port priority and not check packet?s content vlan and tos. table 6 fixed ingress bandwidth control 000 001 010 011 100 101 110 111 256k 512k 1m 2m 5m 10m 20m 50m
samurai adm6996lc/lcx/lhx function description data sheet 34 rev. 1.31, 2005-12-05 * by vlan first: adm6996lc/lcx/lhx check vlan three priority bit first then ip tos priority bits. * by ip tos first: adm6996lc/lcx/lhx check ip tos three priority bit first then vlan three priority bits. if port set at vlan/tos priority but receiving packet without vlan or tos information then port base priority will be used. * by tcp/udp destination port number: adm6996lc/lcx/lhx check layer4 tcp/udp destination port number to map the priority queue. * by mac destination address: user can set mac address to map priority queue. 3.23 led display three leds per port are provided by adm6996lc/lcx/lhx. link/act, duplex/col. & speed are three led display of adm6996lc/lcx/lhx. dual color led mode also supported by adm6996lc/lcx/lhx. for easy production purpose adm6996lc/lcx/lhx will send test signal to each led at power on reset stage. eeprom register 12 h define led configuration table. 1. led_mode : it is the value latched on the edi pin during the power on reset. it?s also used to control the dual or single color mode and is useless when the value wait_init is high. 2. dcs (see 0012 h ): dupcol leds indicate the duplex status only. 3. dhcol (see 0030 h ): when enabled, pin dupcol0 shows col_10m status and pin dupcol1 shows col_100m status. these two leds are necessary in the dual-speed hub. adm6996lc/lcx/lhx led is active low signal. dupcol0 & dupcol1 will check external signal at reset time. if external signal add pull high then led will active low. if external signal add pull down resister then led will drive high. 3.23.1 single color led display table 7 single color led display pin name status lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 these pins have no power on reset values on them, and adm6996lc/lcx/lhx uses active low value to drive the led. so the output values of these pins after the power on reset are shown as follows: 1. first period: this period lasts 1.28 s for led on test. adm6996lc/lcx/lhx drives value 0 to open the led. 2. second period: this period lasts 0.48 s for led off test. adm6996lc/lcx/lhx drives value 1 to close the led. 3. normal period: tis period indicates the link status. 0 b port links up and led is on. 1 b port links down and led is off. 0/1 b port links up and is transmitting or receiving. the led flashes at 10 hz. ldspd4/ldspd3/ ldspd2/ldspd1/ ldspd0 the behavior of these pins is the same as the lnkact, except the normal period. normal period: this period indicates the speed status. 0 b port links up and its speed is 100m. led is on. 1 b port links down or its speed is 10m. led is off.
data sheet 35 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.23.2 dual color led display users should be careful that dupcol led only supports the single color mode. the only difference between single and dual color for dupcol led is the self-test time. dupcol2/ dupcol1/ dupcol0 these 3 pins have power on reset values on them. adm6996lc/lcx/lhx needs to consider these values to drive the correct value. if the power on reset value is value_power_on, then the display is as follows: 1. first period: this period lasts 1.28 s for led on test. adm6996lc/lcx/lhx drives ~value_power_on to open the led. 2. second period: this period lasts 0.48 s for led off test. adm6996lc/lcx/lhx drives value_power_on to close the led. 3. normal period: tis period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led flashes at 10 hz. 0/1 b port links up and collision is detected. the led flashes at 10 hz. if dcs is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b this value is cancelled. led doesn?t blink. if dhcol is enabled, the display in the normal period is as follows: dupcol0: 10m collision indicator. 0/1 b one of the ports links up in 10m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = when the above event is not satisfied, the led is off. dupcol1: 100 m collision indicator. 0/1 b one of the ports links up in 100m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = the above event is not satisfied. led is off. dupcol4/ dupcol3 the behavior of these pins is the same as the lnkact, except for the normal period. normal period: this period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led is off. 0/1 b port links up and collision is detected. the led flashes at 10 hz. if dcs is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b this value is cancelled. led doesn?t blink. table 7 single color led display (cont?d) pin name status
samurai adm6996lc/lcx/lhx function description data sheet 36 rev. 1.31, 2005-12-05 3.23.3 circuit for single led mode figure 3 circuit for single color led mode 3.23.4 circuit for dual led mode figure 4 circuit for dual color led mode table 8 dual color led display pin name status (lnkact4, ldspd4)/ (lnkact3, ldspd3) (lnkact2, ldspd2) (lnkact1, ldspd1) (lnkact0, ldspd0) first period: test led on with green color. it lasts 1.28 s. 01 b led is on with green color. second period: test led on with yellow color. it lasts 1.28 s. 10 b led is on with yellow color. third period: test led off. 00 b led is off. normal period: this period shows the status of the link and speed at the same time. 00 b port links down.led is off. 11 b port links down. led is off. 01 b port links up in 100m. led glows green. 10 b port links up in 10m. led glows yellow. 0/1,1 b port links up in 100m and is receiving or transmitting. led blinks with green color at 10 hz. 0/1,0 b port links up in 10m and is receiving or transmitting. led blinks with yellow color at 10 hz. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 the behavior of these pins is the same as the single mode, except the self-test period. the led on test period is 2.56 s instead of 1.28 s. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0/ lnkact4/lnkact3 lnkact2/lnkact1 lnkact0/ l d spd 4/ l d spd 3 l d spd 2/ l d spd 1 ldspd0/ dupcol2/dupcol1/ dupcol0 3.3v 0v l d spd 4/ l d spd 3/ l d spd 2/ l d spd 1/ ldspd0 lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 3.3v 0v dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 dupcol2/dupcol1/ dupcol0
data sheet 37 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description 3.24 mac clone and port5 mii connection in adm6996lc/lcx, there are three different configurations (mac type mii mode, gpsi mode and rmii, p5_busmd0 ) for port5 to connect the cpu?s mii/gpsi or rmii interface. here we dipicted a general router applications of adm6996lc/lcx, connected to cpu with single mii. in figure 5 , we can see either lan to wan or wan to lan, the packets will go through the same mii port. because the cpu need to send out the packets with the registered mac id to the wan port, and this mac id may also come in from the lan ports. we know the switch learning scheme can?t permit the packets with same mac id input from different port. in the adm6996lc/lcx design, we use the mac clone and vlan group to solve this problem. from figure 6 , users can have more details for this implementation. figure 5 adm6996lc/lcx to cpu with single mii connection 6 port switch core cpu with single mii mii p0 phy p0 mac p1 phy p1 mac p2 phy p2 mac p3 phy p3 mac p4 phy p4 mac p5 mac lan ports wan port mac mii
samurai adm6996lc/lcx/lhx function description data sheet 38 rev. 1.31, 2005-12-05 here we use an example to describe how to enable the mac clone and set the vlan group to reach this lan/wan routing activity. figure 6 mac clone enable and vlan setting step1: set adm6996lc/lcx to tag-based vlan mode -- set eeprom 0x11 h to 0xff20 h step2: set per port pvid and tag/untag output port -- port0, untag, pvid=1, set eeprom 0x01 h to 0x840f h port1, untag, pvid=1, set eeprom 0x03 h to 0x840f h port2, untag, pvid=1, set eeprom 0x05 h to 0x840f h port3, untag, pvid=1, set eeprom 0x07 h to 0x840f h port4, untag, pvid=2, set eeprom 0x08 h to 0x880f h port5, tag, pvid=2, set eeprom 0x09 h to 0x881f h step3: set wan/lan group group1: port 0/1/2/3/5, set eeprom 0x14 h to 0x0155 h group2: port 4/5, set eeprom 0x15 h to 0x0180 h if untag packet received from lan port and forwards to cpu port, adm6996lc/lcx will use ingress port pvid as the egress tag vid. cpu can recognize the source group of the packet by vid. if vid=1, it means the packet is received from the lan port. otherwise, if vid=2, it means the packet is received from the wan port. cpu has to change the tag vid to determine the destination group. the tag packet received from cpu port will follow tag-based vlan to determine the broadcast domain. if the tag packet with vid=1 will follow vlan group 1 (lan group) and the tag packet with vid=2 will follow the vlan group 2 (wan group). cpu port 5 mii, tag, pvid=2 port 0 untag pvid=1 port 1 untag pvid=1 port 2 untag pvid=1 port 3 untag pvid=1 port 4 untag pvid=2 mii lan port wan port 1) untag packet 2) tag packet with vid=1 3) cpu changes vid=1 to 2 4) tag packet with vid=2 5) untag packet
data sheet 39 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx function description normally, the mac mode mii should be connected to the pcs mode mii. but in some applications, we need to connect both mac mode mii to each other as shown in above figures. in figure 7 , due to most cpu?s mii being mac mode, so port5 is mac to mac connected. through the hardware setting, it is easy to set adm6996lc/lcx port5 mii to operate in 100m full duplex mode. this mode (100m full) is normally the operation mode to be with cpu, the interface connection is described in the following diagram. (1) cko25m is the 25m clock driven out by adm6996lc/lcx to fit 100m mii operation. this clock output provides 8ma driving capability and it can directly connected to txclk/rxclk. (2) due to it is operated in full duplex mode, so col is tied to gnd. figure 7 100m full duplex mac to mac mii connection note: 1. pin 60 and pin 61 should be pull low to let p5_busmd be latched as ?00? and make port5 be operating in mii mode ( p5_busmd0 ). 2. pin 89 (spdtnp5) should be pull low or floating to set port5 be operating in 100mbit/s. 3. pin 91 (dphalfp5) should be pull low or floating to set port5 be operating in full duplex mode. 4. pin 90 (lnkfp5) should be pull low or floating to set port5 link up. (85) cko25m (67) txclk (72) rxclk (77) crs (73) rxdv (66) txen (102,101,100,74)rxd[3:0] (59,60,61,63)txd[3:0] (78) col (68) rxer adm6996lc/i p5 mac mode mii txclk rxclk txen crs rxdv txd[3:0] rxd[3:0] col rxer cpu mac mode mii p5_busmd0 (61) spdtnp5 (89) dphalfp5 (91) lnkfp5 (90) note p5_busmd1 (60)
samurai adm6996lc/lcx/lhx function description data sheet 40 rev. 1.31, 2005-12-05 3.25 the hardware difference between adm6996lc/lcx/i and adm6996l adm6996lc/lcx is power-down version to replace adm6996l and adm6996i is advanced function version to new application. pin description(qfp128) table 9 pin description(qfp128) pin no. adm6996lc/lcx adm6996l notes 47 gndik(gnd digital) nc gndik in adm6996l datasheetask the customer to double-check 48 vccik(1.8v digital) nc vccik in adm6996l datasheetask the customer to double-check 59 p5txd3(sdio_md) p5txd3(vol23) for adm6996lc/lcx, sdio_md=0 default 32bit modefor adm6996i, sdio_md=0 default 16bit modeadd pull-up/down resistor for adm6996l/lc/i compatible design to avoid wrong power-on-latch. 60 p5txd2(rmiisel) p5txd2(romcode25 ) add pull down resistor for adm6996l/lc/i p5 mii mode to avoid wrong power-on-latch. 61 p5txd1(7wire) p5txd1(p5gpsi) add pull down resistor for adm6996l/lc/i p5 mii mode to avoid wrong power-on-latch. 65 int_n vccik(1.8v digital) interrupt for learning table access/port security/counter overflow/port statusadd a option design to cpu int_n pin
data sheet 41 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 4 32 bits mode registers description 4.1 eeprom registers (0x0b[0]=0) table 10 registers address space module base address end address note eeprom 00 h 33 h independent address space table 11 registers overview register short name register long name offset address page number sigreg signature register 00 h 43 ctrlreg_0 basic control register 0 01 h 44 resreg_0 reserved register 0 02 h 45 ctrlreg_p1 basic control register 1 03 h 45 resreg_1 reserved register 1 04 h 45 ctrlreg_p2 basic control register 2 05 h 45 resreg_2 reserved register 2 06 h 45 ctrlreg_p3 basic control register 3 07 h 45 ctrlreg_p4 basic control register 4 08 h 45 resreg_3 reserved register 3 09 h 45 resreg_4 reserved register 4 0a h 46 configreg_1 configuration register 1 0b h 46 resreg_5 reserved register 5 0c h 46 resreg_6 reserved register 6 0d h 47 vlan_map_p vlan priority map register 0e h 47 tos_priority tos priority map register 0f h 48 configreg_2 configuration register 2 10 h 48 vlan_mode vlan mode select register 11 h 49 configreg_3 miscellaneous configuration register 3 12 h 52 vlan_map_0 vlan mapping table registers 0 13 h 53 vlan_map_1 vlan mapping table registers 1 14 h 54 vlan_map_2 vlan mapping table registers 2 15 h 54 vlan_map_3 vlan mapping table registers 3 16 h 54 vlan_map_4 vlan mapping table registers 4 17 h 54 vlan_map_5 vlan mapping table registers 5 18 h 54 vlan_map_6 vlan mapping table registers 6 19 h 54 vlan_map_7 vlan mapping table registers 7 1a h 54 vlan_map_8 vlan mapping table registers 8 1b h 54 vlan_map_9 vlan mapping table registers 9 1c h 54 vlan_map_10 vlan mapping table registers 10 1d h 54
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 42 rev. 1.31, 2005-12-05 the register is addressed wordwise. vlan_map_11 vlan mapping table registers 11 1e h 54 vlan_map_12 vlan mapping table registers 12 1f h 54 vlan_map_13 vlan mapping table registers 13 20 h 54 vlan_map_14 vlan mapping table registers 14 21 h 54 vlan_map_15 vlan mapping table registers 15 22 h 54 resreg_7 reserved register 7 23 h 54 resreg_8 reserved register 8 24 h 55 resreg_9 reserved register 9 25 h 55 resreg_10 reserved register 10 26 h 55 resreg_11 reserved register 11 27 h 55 configreg_4 configuration register 4 28 h 55 configreg_5 configuration register 5 29 h 55 configreg_6 configuration register 6 2a h 56 configreg_7 configuration register 7 2b h 56 configreg_8 configuration register 2c h 56 resreg_12 reserved register 12 2d h 57 resreg_13 reserved register 13 2e h 58 ph_restart phy restart 2f h 58 configreg_ miscellaneous configuration register 9 30 h 59 bwcon_0 bandwidth control register 0 31 h 59 bwcon_1 bandwidth control register 1 32 h 60 bwconen bandwidth control enable register 33 h 61 table 12 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) table 11 registers overview (cont?d) register short name register long name offset address page number
data sheet 43 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 4.1.1 eeprom register descriptions signature register description latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interrupt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be cleared due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 13 registers clock domains clock short name description ?? sigreg offset reset value signature register 00 h 4154 h field bits type description signature 15:0 ro signature 4154 h sigreg obligatory value (at) table 12 register access types (cont?d) mode symbol description hw description sw ur 6ljqdwxuh
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 44 rev. 1.31, 2005-12-05 note: adm6996lc/lcx/lhx will check register 0 value before read all eeprom content. if this value not match with 0x4154h then other values in eeprom will be useless. adm6996lc/lcx/lhx will use internal default value. user cannot write signature register when programming adm6996lc/lcx/lhx internal register. basic control register 0 used to configure chip settings ctrlreg_0 offset reset value basic control register 0 01 h 040f h field bits type description cam 15 rw crossover auto mdix 0 b d disable note: hardware reset latch value eesk can be set globally using the auto mdix function. 1 b e enable fse 14 rw fx select enable 0 b tp tp mode note: if this bit has been set to fx in hardware then the bit does not have the power to change from fx to tp 1 b fx fx mode pv 13 :10 rw port vlan id pp 9:8 rw port based priority ppe 7 rw port based priority enable 0 b vte vlan or tos priority enable note: this bit is default 0 b to enable vlan or tos priority check. if user would like to check the vlan priority, tag mode should be enabled. 1 b pbe port based priority enable note: if this bit is set to 1 b , only port based priority will be checked. tv 6 rw tos over vlan priority 0 b v vlan enable 1 b t tos enable pd 5 rw port disable 0 b e enable 1 b d disable ot 4 rw output packet tagging 0 b u un-tag 1 b t tag uz &$0 uz )6( uz 39 uz 33 uz 33( uz 79 uz 3' uz 27 uz '83 uz 236 uz $1 uz )&
data sheet 45 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description similar registers reserved register 0 register reserved for future use similar registers dup 3 rw duplex enable 0 b h half 1 b f full ops 2 rw operating speed 0 b 10 10 mbit/s 1 b 100 100 mbit/s an 1 rw auto-negotiation 0 b d disable 1 b e enable fc 0 rw 802.x flow control command 0 b d disable 1 b e enable table 14 basic control registers 1 to 4 register short name register long name offset address page number ctrlreg_p1 basic control register 1 03 h ctrlreg_p2 basic control register 2 05 h ctrlreg_p3 basic control register 3 07 h ctrlreg_p4 basic control register 4 08 h resreg_0 offset reset value reserved register 0 02 h 040f h field bits type description res 15:0 ro reserved table 15 reserved register 1 to 3 register short name register long name offset address page number resreg_1 reserved register 1 04 h resreg_2 reserved register 2 06 h resreg_3 reserved register 3 09 h field bits type description ur 5hv
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 46 rev. 1.31, 2005-12-05 reserved register 4 register reserved for future use configuration register 1 used to configure the chip reserved register 5 reserved for future use resreg_4 offset reset value reserved register 4 0a h 5902 h field bits type description res 15:10 ro reserved idr 9 rw replace packet id 0 b n not replaced 1 b y replaced with 1 by pvid res 8:0 ro reserved configreg_1 offset reset value configuration register 1 0b h 8000 h field bits type description fd 15 rw far end fault detection 0 b d disable 1 b e enable res 14:8 ro reserved te 7 rw trunk enable 0 b d disable port 3 and 4 1 b e enable port 3 and 4 ipg 6 rw inter packet gap setting 0 b 96b 96 bits 1 b 92b 92 bits res 5:0 ro reserved ur 5hv uz ,'5 ur 5hv uz )' ur 5hv uz 7( uz ,3* ur 5hv
data sheet 47 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description similar registers vlan priority map register sets the vlan priorities note: value 3 ~ 0 are for priority queue q3~q0 respectively.the weight ratio is q3: q2: q1: q0 = 8: 4: 2: 1. the default is port-base priority for un-tagged packets and non_ip frame. resreg_5 offset reset value reserved register 5 0c h fa50 h field bits type description res 15:0 ro reserved table 16 reserved register 6 register short name register long name offset address page number resreg_6 reserved register 6 0d h vlan_map_p offset reset value vlan priority map register 0e h 5500 h field bits type description v7 15:14 rw mapped priority of tag value (vlan) v6 13:12 rw v5 11:10 rw v4 9:8 rw v3 7:6 rw v2 5:4 rw v1 3:2 rw v0 1:0 rw ur 5hv uz 9 uz 9 uz 9 uz 9 uz 9 uz 9 uz 9 uz 9
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 48 rev. 1.31, 2005-12-05 type of service (tos) priority map register sets tos priority note: value 3 ~ 0 are for priority queues q3~q0 respectively. the weight ratio is q3: q2: q1: q0 = 8: 4: 2: 1. the default is port-based priority for un-tagged packets and non_ip frames. configuration register 2 used to configure the chip tos_priority offset reset value tos priority map register 0f h 5500 h field bits type description t7 15:14 rw mapped priority of tag value (tos) t6 13:12 rw t5 11:10 rw t4 9:8 rw t3 7:6 rw t2 5:4 rw t1 3:2 rw t0 1:0 rw configreg_2 offset reset value configuration register 2 10 h 0040 h field bits type description q3 15:14 rw discard mode drop scheme for queue n. see table 19 for details on the drop scheme of each queue q2 13:12 rw q1 11:10 rw q0 9:8 rw uz 7 uz 7 uz 7 uz 7 uz 7 uz 7 uz 7 uz 7 uz 4 uz 4 uz 4 uz 4 uz $*( ur 5hv uz ;& uz 5hv uz 6) uz 67
data sheet 49 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description note: broadcast storm initial time interval = 50ms. the max. packet number = 7490 in 100base, 749 in 10base vlan mode select register selects vlan mode age 7 rw aging status 0 b e enable 1 b d disable res 6:5 ro reserved xc 4 rw crc check 0 b e enable crc check 1 b d disable crc check res 3 rw reserved sf 2 rw broadcast storm filter 0 b d disable 1 b e enable st 1:0 rw broadcast storm threshold see below table 17 and table 18 for details on the broadcast storm threshold table 17 the max. packet number = 7490 in 100base, 749 in 10base per port rising threshold 00 b 01 b 10 b 11 b all 100tx disable 14880fps 29760fps 59520fps not all 100tx disable 1488fps 2976fps 5952fps table 18 the max. packet number = 7490 in 100base, 749 in 10base per port falling threshold 00 b 01 b 10 b 11 b all 100tx disable 7440fps 14880fps 29760fps not all 100tx disable 744fps 1488fps 2976fps table 19 drop scheme for each queue discard mode utilization 00 01 10 11 tbd 0% 0% 25% 50% vlan_mode offset reset value vlan mode select register 11 h ff00 h field bits type description
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 50 rev. 1.31, 2005-12-05 note: below is an example of a vlan tag and a mac application for bit4 and bit5. below is an old router architecture example. the disadvantages of this are: 1. wan port only supports 10m half-duplex and non-mdix functions 2. needs extra 10m nic cost. 3. isa bus will become a bottleneck for the whole system figure 8 old router architecture example below is new architecture by using adm6996lc/lcx/lhx serial chip vlan function. the advantages of below are: 1. wan port can upgrade to 100/10 full/half, auto mdix. 2. wan/lan port is programmable and put on same switch. field bits type description res 15:6 ro reserved vm 5 rw vlan mode select 0 b p port based by-pass mode 1 b q 802.1q based mac 4 rw mac clone enable 0 b n normal mode.learning with sa only. the mac table will be searched or filled using only sa or da. 1 b m mac mode. learned using sa vid0. mac table will be searched or filled using vid0 sa or da. this bit allows two identical addresses with different vid0 to be learned. res 3:0 ro reserved ur 5hv uz 90 uz 0$& ur 5hv cpu with one mii 10m half nic isa bus port4 mac mii port port0 port1 port2 port3 mii 4 10/100m lan port 10m half non-mdix wan port
data sheet 51 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 3. no need extra nic and save lot of cost. 4. high bandwidth of mii port up to 200m speed. figure 9 new router architectu re using adm6996lc/lcx/lhx new router application works well on normal application. if user?s isp vendor(cable modem) lock registration card?s id then router cpu must send this lock registration card?s id to wan port. one condition happen is there exist two same mac id on this switch. one is original card and another one is cpu. this will make switch learning table trouble. adm6996lc/lcx/lhx provide mac clone function that allow two same mac address with different vlan id0 on learning table. this will solve lock registration card?s id issue. adm6996 series chip will put these two same mac addresses with different vlan id0 at different learning table entry. how to set adm6996lc/lcx/lhx on router port0~3: lan port. port4: wan port. port5: mii port as cpu port. step1: set register 0x11h bit4 and bit5 to 1. {coding: write register 0x11h as 0xff30h} step2: set port0~3 as untag port and set pvid=1. {coding: write register 0x01h, 0x03h, 0x05h, 0x07h as 0x840f. port0~3 as untag, pvid=1, enable mdix} step3: set port4 as untag port and set pvid=2. {coding:write register 0x08h as 0x880fh. port4 as untag, pvid=2, enable mdix.} step4: set port5 mii port as tag port and set pvid=2. {coding:write register 0x09h as 0x881fh. port5 mii port as tag, pvid=2.} step5: group port0, 1, 2, 3, 5 as vlan 1. {coding: write register 0x14h as 0x0155h. vlan1 cover port0, 1, 2, 3, 5.} step6: group port4, 5 as vlan 2. {coding: write register 0x15h as 0x0180h. vlan2 cover port4, 5.} how mac clone operation ? lan to lan/cpu traffic. adm6996lc/lcx/lhx lan traffic to lan/cpu only. traffic to another lan port will be cpu with one mii port5 mac mii port port0 mii 4 10/100m lan port 10/100m wan port port1 port2 port3 port4
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 52 rev. 1.31, 2005-12-05 untag packet. traffic to cpu is tag packet with vid=1. cpu can check vid to distinguish lan traffic or wan traffic. ? wan to cpu traffic. adm6996lc/lcx/lhx wan traffic to cpu only. traffic to cpu is tag packet with vid=2. cpu can check vid to distinguish lan traffic or wan traffic. ? cpu to lan packet. adm6996lc/lcx/lhx cpu packet to lan port must add vid=1 in vlan field. adm6996lc/lcx/lhx check vid to distinguish lan traffic or wan traffic. lan output packet is untag. ? cpu to wan packet. adm6996lc/lcx/lhx cpu packet to wan port must add vid=2 in vlan filed. adm6996lc/lcx/lhx check vid to distinguish lan traffic or wan traffic. wan output packet is untag. ? adm6996lc/lcx/lhx learning sequence adm6996lc/lcx/lhx will check vlan mapping setting first then check learning table. user does not worry lan/wan traffic mix up. bit 10: half duplex back pressure enable. 1/enable, 0/disable. configuration register 3 configreg_3 offset reset value miscellaneous configuration register 3 12 h 3600 h field bits type description cd 15 rw excessive collision drop 0 b d disable 1 b e enable dcs 14 rw duplex and col separate 0 b d indicate the duplex and collision status at the same time 1 b lm indicate the duplex status only res 13:9 rw reserved ml5 8 rw port5 mac lock 0 b d disable 1 b lm lock first mac source address ml4 7 rw port4 mac lock 0 b d disable 1 b lm lock first mac source address uz &' uz '&6 uz 5hv uz 0/ uz 0/ uz 0/ uz 5hv uz 0/ uz 5hv uz 0/ uz 5hv uz 0/
data sheet 53 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description vlan mapping table registers 0 ml3 6 rw port3 mac lock 0 b d disable 1 b lm lock first mac source address res 5 rw reserved ml2 4 rw port 2 mac lock 0 b d disable 1 b lm lock first mac source address res 3 rw reserved ml1 2 rw port1 mac lock 0 b d disable 1 b lm lock first mac source address res 1 rw reserved ml0 0 rw port0 mac lock 0 b d disable 1 b lm lock first mac source address vlan_map_0 offset reset value vlan mapping table registers 0 13 h ffff h field bits type description res 15:9 ro reserved vm5 8 rw port 5 vlan mapping 0 b nm port 5 is not the member of the vlan. 1 b m port 5 is the member of the vlan. vm4 7 rw port 4 vlan mapping 0 b nm port 4 is not the member of the vlan. 1 b m port 4 is the member of the vlan. vm3 6 rw port 3 vlan mapping 0 b nm port 3 is not the member of the vlan. 1 b m port 3 is the member of the vlan. res 5 ro reserved vm2 4 rw port 2 vlan mapping 0 b nm port 2 is not the member of the vlan. 1 b m port 2 is the member of the vlan. res 3 ro reserved field bits type description ur 5hv uz 90 uz 90 uz 90 ur 5hv uz 90 ur 5hv uz 90 ur 5hv uz 90
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 54 rev. 1.31, 2005-12-05 note: 16 vlan group: see register 0x2ch bit 11. select the vlan group ports and set the corresponding bits to 1. similar registers reserved register 7 vm1 2 rw port 1 vlan mapping 0 b nm port 1 is not the member of the vlan. 1 b m port 1 is the member of the vlan. res 1 ro reserved vm0 0 rw port 0 vlan mapping 0 b nm port 0 is not the member of the vlan. 1 b m port 0 is the member of the vlan. table 20 vlan mapping table registers 1 to 15 register short name register long name offset address page number vlan_map_1 vlan mapping table registers 1 14 h vlan_map_2 vlan mapping table registers 2 15 h vlan_map_3 vlan mapping table registers 3 16 h vlan_map_4 vlan mapping table registers 4 17 h vlan_map_5 vlan mapping table registers 5 18 h vlan_map_6 vlan mapping table registers 6 19 h vlan_map_7 vlan mapping table registers 7 1a h vlan_map_8 vlan mapping table registers 8 1b h vlan_map_9 vlan mapping table registers 9 1c h vlan_map_10 vlan mapping table registers 10 1d h vlan_map_11 vlan mapping table registers 11 1e h vlan_map_12 vlan mapping table registers 12 1f h vlan_map_13 vlan mapping table registers 13 20 h vlan_map_14 vlan mapping table registers 14 21 h vlan_map_15 vlan mapping table registers 15 22 h resreg_7 offset reset value reserved register 7 23 h 0000 h field bits type description uz 5hv
data sheet 55 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description similar registers configuration register 4 configuration register 5 field bits type description res 15:0 rw reserved table 21 reserved register 8 to 11 register short name register long name offset address page number resreg_8 reserved register 8 24 h resreg_9 reserved register 9 25 h resreg_10 reserved register 10 26 h resreg_11 reserved register 11 27 h configreg_4 offset reset value configuration register 4 28 h 0000 h field bits type description res 15:8 ro reserved p0 7:0 rw port 0 pvid 0001 h pvid these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. configreg_5 offset reset value configuration register 5 29 h 0000 h field bits type description res 15:8 ro reserved ur 5hv uz 3 ur 5hv uz 3
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 56 rev. 1.31, 2005-12-05 configuration register 6 configuration register 7 configuration register 8 p1 7:0 rw port1 pvid bit 11~4. 0003 h pvid 1 these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. configreg_6 offset reset value configuration register 6 2a h 0000 h field bits type description res 15:8 ro reserved p2 7:0 rw port2 pvid bit 11~4. 0005 h pvid 2 these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. configreg_7 offset reset value configuration register 7 2b h 0000 h field bits type description p4 15:8 ro port4 pvid bit 11~4. 0008 h pvid 1 these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. p3 7:0 rw port3 pvid bit 11~4. 0007 h pvid 1 these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. field bits type description ur 5hv uz 3 ur 3 uz 3
data sheet 57 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description note: bit[10:8]: vlan tag shift register. adm6996lc/lcx/lhx will select 4 bit form total 12 bit vid as vlan group reference. bit[15:12]: ieee 802.3 reserved da forward or drop police. reserved register 12 configreg_8 offset reset value configuration register 2c h d000 h field bits type description cr0 15 rw control reserved mac control reserved mac (0180c2000000) 0 b d discard 1 b f forward cr1 14 rw control reserved mac control reserved mac (0180c2000001) 0 b d discard 1 b f forward cr2 13 rw control reserved mac control reserved mac (0180c2000002- 0180c200000f) 0 b d discard 1 b f forward cr3 12 rw control reserved mac control reserved mac (0180c2000010-0180c20000ff) 0 b d discard 1 b f forward res 11 rw reserved vs 10:8 rw vlan grouping tag shift 0 d vid0 vid [3:0] 1 d vid1 vid [4:1] 2 d vid2 vid [5:2] 3 d vid3 vid [6:3] 4 d vid4 vid [7:4] 5 d vid5 vid [8:5] 6 d vid6 vid [9:6] 7 d vid7 vid [10:7] p5 7:0 rw port5 pvid bit 11~4. 0009 h pvid 1 these 8 bits combine with the register in the hex values bit?s [13~10] as the full 12 bits of the vid. uz &5 uz &5 uz &5 uz &5 uz 5hv uz 96 uz 3
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 58 rev. 1.31, 2005-12-05 reserved register 13 phy restart resreg_12 offset reset value reserved register 12 2d h 4442 h field bits type description res 15:0 rw reserved resreg_13 offset reset value reserved register 13 2e h 0000 h field bits type description res 15:0 rw reserved ph_restart offset reset value phy restart 2f h 0000 h field bits type description pr 15:0 rw phy restart 0000 h phy restart writing this hex value to this register restarts the internal phys. uz 5hv uz 5hv uz 35
data sheet 59 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description configuration register 9 bandwidth control register configreg_ offset reset value miscellaneous configuration register 9 30 h 0987 h field bits type description res 15:13 rw reserved lm 12 rw port 4 led mode 0 b d linkact/dupcol/speed 1 b s linkact/speed res 11 rw reserved res 10 rw reserved dhcol 9 rw dual speed hub col_led enable 0 b n normal led display. 1 b d dual speed hub led display. port0 col led: 10m col led. port1 col led: 100m col led. res 8:7 rw reserved rcl 6 rw mii speed double 0 b 25 txclk max speed is 25 mhz 1 b 50 txclk max speed is 50 mhz mac 5 rw mac clone enable mac clone enable bit[1]. res 4:0 rw reserved bwcon_0 offset reset value bandwidth control register 0 31 h 0000 h uz 5hv uz /0 uz 5hv uz 5hv uz '+&2 / uz 5hv uz 5&/ uz 0$& uz 5hv uz 5& uz 37 uz 5& uz 37 uz 5& uz 37 uz 5& uz 37
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 60 rev. 1.31, 2005-12-05 bandwidth control register 1 field bits type description rc3 15 rw receive packet length count counted on the source port 3. 0 d r3 the switch will add length to the p3 counter p3t 14:12 rw port 3 threshold control meter reference table 22 in note below. rc2 11 rw receive packet length count counted on the source port 2. 0 d r2 the switch will add length to the p2 counter p2t 10:8 rw port 2 threshold control meter reference table 22 in note below. rc1 7 rw receive packet length count counted on the source port 1. 0 d r1 the switch will add length to the p1 counter p1t 6:4 rw port 1 threshold control meter reference table 22 in note below. rc0 3 rw receive packet length count counted on the source port 0. 0 d r0 the switch will add length to the p2 counter p0t 2:0 rw port 0 threshold control meter reference table 22 in note below. table 22 note: reference table 000 001 010 011 100 101 110 111 256k 512k 1m 2m 5m 10m 20m 50m bwcon_1 offset reset value bandwidth control register 1 32 h 0000 h field bits type description res 15:8 ro reserved rc5 7 rw receive packet length count counted on the source port 5. 0 d count5 the switch will add length to the p5 counter ur 5hv uz 5& uz 37 uz 5& uz 37
data sheet 61 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description bandwidth control enable register p5t 6:4 rw port 5 threshold control meter reference table 22 in note below. rc4 3 rw receive packet length count counted on the source port 4. 0 d count4 the switch will add length to the p4 counter p4t 2:0 rw port 4 threshold control meter reference table 22 in note below. bwconen offset reset value bandwidth control enable register 33 h 0000 h field bits type description res 15:9 ro reserved bw5 8 rw port 5 bandwidth control enable 0 b d disable 1 b e enable bw4 7 rw port 4 bandwidth control enable 0 b d disable 1 b e enable bw3 6 rw port 3 bandwidth control enable 0 b d disable 1 b e enable res 5 rw reserved bw2 4 rw port 2 bandwidth control enable 0 b d disable 1 b e enable res 3 rw reserved bw1 2 rw port 1 bandwidth control enable 0 b d disable 1 b e enable res 1 rw reserved bw0 0 rw port 0 bandwidth control enable 0 b d disable 1 b e enable field bits type description ur 5hv uz %: uz %: uz %: uz 5hv uz %: uz 5hv uz %: uz 5hv uz %:
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 62 rev. 1.31, 2005-12-05 4.2 serial registers table 23 registers address space module base address end address note serial registers 00 h 3c h independent address space table 24 registers overview register short name register long name offset address page number chipid chip identifier register 00 h 63 portstat_0 port status register 0 01 h 63 portstat_1 port status register 1 02 h 65 cabstat cable broken status 03 h 66 p0_rp_cnt port 0 receive packet count 04 h 66 p1_rp_cnt port 1 receive packet count 06 h 67 p2_rp_cnt port 2 receive packet count 08 h 67 p3_rp_cnt port 3 receive packet count 0a h 67 p4_rp_cnt port 4 receive packet count 0b h 67 p5_rp_cnt port 5 receive packet count 0c h 67 p0_rb_cnt port 0 receive byte count 0d h 67 p1_rb_cnt port 1 receive byte count 0f h 67 p2_rb_cnt port 2 receive byte count 11 h 67 p3_rb_cnt port 3 receive byte count 13 h 67 p4_rb_cnt port 4 receive byte count 14 h 67 p5_rb_cnt port 5 receive byte count 15 h 67 p0_tp_cnt port 0 transmit packet count 16 h 67 p1_tp_cnt port 1 transmit packet count 18 h 67 p2_tp_cnt port 2 transmit packet count 1a h 67 p3_tp_cnt port 3 transmit packet count 1c h 67 p4_tp_cnt port 4 transmit packet count 1d h 67 p5_tp_cnt port 5 transmit packet count 1e h 67 p0_tb_cnt port 0 transmit byte count 1f h 67 p1_tb_cnt port 1 transmit byte count 21 h 67 p2_tb_cnt port 2 transmit byte count 23 h 67 p3_tb_cnt port 3 transmit byte count 25 h 67 p4_tb_cnt port 4 transmit byte count 26 h 67 p5_tb_cnt port 5 transmit byte count 27 h 67 p0_col_cnt port 0 collision count 28 h 67 p1_col_cnt port 1 collision count 2a h 67 p2_col_cnt port 2 collision count 2c h 67 p3_col_cnt port 3 collision count 2e h 67 p4_col_cnt port 4 collision count 2f h 67 p5_col_cnt port 5 collision count 30 h 67
data sheet 63 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description the register is addressed wordwise. for register access types see table 12 ?register access types? on page 42 . 4.2.1 serial register map chip identifier register port status register 0 p0_err_cnt port 0 error count 31 h 67 p1_err_cnt port 1 error count 33 h 68 p2_err_cnt port 2 error count 35 h 68 p3_err_cnt port 3 error count 37 h 68 p4_err_cnt port 4 error count 38 h 68 p5_err_cnt port 5 error count 39 h 68 overflow_0 over flow flag register 0 3a h 68 overflow_1 over flow flag register 1 3b h 68 overflow_2 over flow flag register 2 3c h 69 table 25 registers clock domains clock short name description ?? chipid offset reset value chip identifier register 00 h 0007 1022 h field bits type description id 31:4 ro chip identifier register 000 7102 h id chip identifier ver 3:0 ro version no 2 h ver version no. portstat_0 offset reset value port status register 0 01 h 0000 0000 h table 24 registers overview (cont?d) register short name register long name offset address page number ur ,' ur 9hu
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 64 rev. 1.31, 2005-12-05 field bits type description fp4 31 ro port 4 flow control enable 0 b d flow control disable 1 b fc4 802.3x on for full duplex or back pressure on for half duplex. dp4 30 ro port 4 duplex status 0 b h half duplex 1 b f full duplex sp4 29 ro port 4 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp4 28 ro port 4 linkup status 0 b ne link is not established. 1 b e link is established. fp3 27 ro port 3 flow control enable 0 b d flow control disable 1 b fc3 802.3x on for full duplex or back pressure on for half duplex. dp3 26 ro port 3 duplex status 0 b h half duplex 1 b f full duplex sp3 25 ro port 3 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp3 24 ro port 3 linkup status port 3 linkup status: 0 b n link is not established. 1 b e link is established. res 23:20 ro reserved fp2 19 ro port 2 flow control enable 0 b d flow control disable 1 b fc2 802.3x on for full duplex or back pressure on for half duplex. dp2 18 ro port 2 duplex status 0 b h half duplex 1 b f full duplex sp2 17 ro port 2 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp2 16 ro port 2 linkup status port 2 linkup status: 0 b ne link is not established. 1 b e link is established. res 15:12 ro reserved ur )3 ur '3 ur 63 ur /3 ur )3 ur '3 ur 63 ur /3 ur 5hv ur )3 ur '3 ur 63 ur /3 ur 5hv ur )3 ur '3 ur 63 ur /3 ur 5hv ur )3 ur '3 ur 63 ur /3
data sheet 65 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description port status register 1 fp1 11 ro port 1 flow control enable 0 b d flow control disable 1 b fc1 802.3x on for full duplex or back pressure on for half duplex. dp1 10 ro port 1 duplex status 0 b h half duplex 1 b f full duplex sp1 9 ro port 1 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp1 8 ro port 1 linkup status 0 b ne not established. 1 b e established. res 7:4 ro reserved fp0 3 ro port 0 flow control enable 0 b d flow control disable 1 b fc0 802.3x on for full duplex or back pressure on for half duplex. dp0 2 ro port 0 duplex status 0 b h half duplex 1 b f full duplex sp0 1 ro port 0 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp0 0 ro port 0 linkup status 0 b ne not established. 1 b e established. portstat_1 offset reset value port status register 1 02 h 0000 0000 h field bits type description res 31:5 ro reserved fp5 4 ro port 5 flow control enable 0 b d flow control disable 1 b fc5 802.3x on for full duplex or back pressure on for half duplex. dp5 3 ro port 5 duplex status 0 b h half duplex 1 b f full duplex field bits type description ur 5hv ur )3 ur '3 ur 63 ur /3
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 66 rev. 1.31, 2005-12-05 cable broken status register port 0 receive packet count sp5 2:1 ro port 5 speed status 0 b 10 10 mbit/s 1 b 100 100 mbit/s lp5 0 ro port 5 linkup status 0 b ne not established. 1 b e established. cabstat offset reset value cable broken status 03 h 0000 0000 h field bits type description res 31:24 ro reserved cb4 23 ro port 4 cable broken cl4 22:21 ro port 4 cable broken length cb3 20 ro port 3 cable broken cl3 19:18 ro port 3 cable broken length res 17:15 ro reserved cb2 14 ro port 2 cable broken cl2 13:12 ro port 2 cable broken length res 11:9 ro reserved cb1 8 ro port 1 cable broken cl1 7:6 ro port 1 cable broken length res 5:3 ro reserved cb0 2 ro port 0 cable broken cl0 1:0 ro port 0 cable broken length p0_rp_cnt offset reset value port 0 receive packet count 04 h 0000 0000 h field bits type description ur 5hv ur &% ur &/ ur &% ur &/ ur 5hv ur &% ur &/ ur 5hv ur &% ur &/ ur 5hv ur &% ur &/
data sheet 67 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description similar registers field bits type description p0_rp_cnt 31:0 ro counter table 26 per port counters register short name register long name offset address page number p1_rp_cnt port 1 receive packet count 06 h p2_rp_cnt port 2 receive packet count 08 h p3_rp_cnt port 3 receive packet count 0a h p4_rp_cnt port 4 receive packet count 0b h p5_rp_cnt port 5 receive packet count 0c h p0_rb_cnt port 0 receive byte count 0d h p1_rb_cnt port 1 receive byte count 0f h p2_rb_cnt port 2 receive byte count 11 h p3_rb_cnt port 3 receive byte count 13 h p4_rb_cnt port 4 receive byte count 14 h p5_rb_cnt port 5 receive byte count 15 h p0_tp_cnt port 0 transmit packet count 16 h p1_tp_cnt port 1 transmit packet count 18 h p2_tp_cnt port 2 transmit packet count 1a h p3_tp_cnt port 3 transmit packet count 1c h p4_tp_cnt port 4 transmit packet count 1d h p5_tp_cnt port 5 transmit packet count 1e h p0_tb_cnt port 0 transmit byte count 1f h p1_tb_cnt port 1 transmit byte count 21 h p2_tb_cnt port 2 transmit byte count 23 h p3_tb_cnt port 3 transmit byte count 25 h p4_tb_cnt port 4 transmit byte count 26 h p5_tb_cnt port 5 transmit byte count 27 h p0_col_cnt port 0 collision count 28 h p1_col_cnt port 1 collision count 2a h p2_col_cnt port 2 collision count 2c h p3_col_cnt port 3 collision count 2e h p4_col_cnt port 4 collision count 2f h p5_col_cnt port 5 collision count 30 h p0_err_cnt port 0 error count 31 h ur 3b53b&17
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 68 rev. 1.31, 2005-12-05 over flow flag register 0 over flow flag register 1 p1_err_cnt port 1 error count 33 h p2_err_cnt port 2 error count 35 h p3_err_cnt port 3 error count 37 h p4_err_cnt port 4 error count 38 h p5_err_cnt port 5 error count 39 h overflow_0 offset reset value over flow flag register 0 3a h 0000 0000 h field bits type description res 31:18 ro reserved or5 17 ro overflow of port 5 receive packet byte count or4 16 ro overflow of port 4 receive packet byte count or3 15 ro overflow of port 3 receive packet byte count res 14 ro reserved or2 13 ro overflow of port 2 receive packet byte count res 12 ro reserved or1 11 ro overflow of port 1 receive packet byte count res 10 ro reserved or0 9 ro overflow of port 0 receive packet byte count of5 8 ro overflow of port 5 receive packet count of4 7 ro overflow of port 4 receive packet count of3 6 ro overflow of port 3 receive packet count res 5 ro reserved of2 4 ro overflow of port 2 receive packet count res 3 ro reserved of1 2 ro overflow of port 1 receive packet count res 1 ro reserved of0 0 ro overflow of port 0 receive packet count table 26 per port counters (cont?d) register short name register long name offset address page number ur 5hv ur 25 ur 25 ur 25 ur 5h v ur 25 ur 5h v ur 25 ur 5h v ur 25 ur 2) ur 2) ur 2) ur 5h v ur 2) ur 5h v ur 2) ur 5h v ur 2)
data sheet 69 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description over flow flag register 2 overflow_1 offset reset value over flow flag register 1 3b h 0000 0000 h field bits type description res 31:18 ro reserved ob5 17 ro overflow of port 5 transmit packet byte count ob4 16 ro overflow of port 4 transmit packet byte count ob3 15 ro overflow of port 3 transmit packet byte count res 14 ro reserved ob2 13 ro overflow of port 2 transmit packet byte count res 12 ro reserved ob1 11 ro overflow of port 1 transmit packet byte count res 10 ro reserved ob0 9 ro overflow of port 0 transmit packet byte count of5 8 ro overflow of port 5 transmit packet count of4 7 ro overflow of port 4 transmit packet count of3 6 ro overflow of port 3 transmit packet count res 5 ro reserved of2 4 ro overflow of port 2 transmit packet count res 3 ro reserved of1 2 ro overflow of port 1 transmit packet count res 1 ro reserved of0 0 ro overflow of port 0 transmit packet count overflow_2 offset reset value over flow flag register 2 3c h 0000 0000 h ur 5hv ur 2% ur 2% ur 2% ur 5h v ur 2% ur 5h v ur 2% ur 5h v ur 2% ur 2) ur 2) ur 2) ur 5h v ur 2) ur 5h v ur 2) ur 5h v ur 2) ur 5hv ur 2( ur 2( ur 2( ur 5h v ur 2( ur 5h v ur 2( ur 5h v ur 2( ur 2) ur 2) ur 2) ur 5h v ur 2) ur 5h v ur 2) ur 5h v ur 2)
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 70 rev. 1.31, 2005-12-05 4.3 packet with priority: normal packet content 4.4 vlan packet note: adm6996lc/lcx/lhx will check packet byte 12 &13. if byte[12:13]=8100h then this packet is a vlan packet byte 14~15: tag control information tci bit[15:13]: user priority 7~0 bit 12: canonical format indicator (cfi) bit[11~0]: vlan id. the adm6996lc/lcx/lhx will use bit[3:0] as vlan group. field bits type description res 31:18 ro reserved oe5 17 ro overflow of port 5 error count oe4 16 ro overflow of port 4 error count oe3 15 ro overflow of port 3 error count res 14 ro reserved oe2 13 ro overflow of port 2 error count res 12 ro reserved oe1 11 ro overflow of port 1 error count res 10 ro reserved oe0 9 ro overflow of port 0 error count of5 8 ro overflow of port 5 collision count of4 7 ro overflow of port 4collision count of3 6 ro overflow of port 3collision count res 5 ro reserved of2 4 ro overflow of port 2 collision count res 3 ro reserved of1 2 ro overflow of port 1 collision count res 1 ro reserved of0 0 ro overflow of port 0 collision count table 27 ethernet packet from layer 2 preamble/sfd destination (6 bytes) source (6 bytes) packet length (2 bytes) data (46-1500 bytes) crc (4 bytes) byte 0~5 byte 6~11 byte 12~13 byte 14~ table 28 vlan packet tag protocol td 8100 tag control information tci len length routing information byte 12~13 byte14~15 byte 16~17 byte 18
data sheet 71 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description 4.5 tos ip packet note: adm6996lc/lcx/lhx checks bytes 12 &13. if this value is 0800h then the adm6996lc/lcx/lhx knows this is a top priority packet. ip header define byte 14 bit[7:0]: ip protocol version number & header length. byte 15: service type bit[7~5]: ip priority (precedence) from 7~0 bit 4: no delay (d) bit 3: high throughput bit 2: high reliability (r) bit[1:0]: reserved 4.6 eeprom access customer can select adm6996lc/lcx/lhx read eeprom contents as chip setting or not. adm6996lc/lcx/lhx will check the signature of eeprom to decide read content of eeprom or not. keep at least 30ms after resetl from 01. adm6996lc/lcx/lhx will read data from eeprom. after resetl if cpu update eeprom that adm6996lc/lcx/lhx will update configuration registers too. when cpu programming eeprom & adm6996lc/lcx/lhx, adm6996lc/lcx/lhx recognizes the eeprom write instruction only. if there is any protection instruction before or after the eeprom write instruction, cpu needs to generate separated cs signal cycle for each protection & write instruction. cpu can directly program adm6996lc/lcx/lhx after 30ms of reset signal rising edge with or without eeprom adm6996lc/lcx/lhx serial chips will latch hardware-reset value as recommend value. it includes eeprom interface: eecs: internal pull down 40k resister. eesk: tp port auto-mdix select. internal pull down 40k resister as non auto-mdix mode. edi: dual color select. internal pull down 40k resister as single color mode. edo: eeprom enable. internal pull up 40k resister as eeprom enable. below figure is adm6996lc/lcx/lhx serial chips eeprom pins operation at different stage. reset signal is control by cpu with at least 100ms low. point1 is reset rising edge. cpu must prepare proper value on eecs(0), table 29 ip packet type 0800 ip header byte 12~13 byte 14~15 table 30 resetl & eeprom content relationship resetl cs sk di do 0 high impedance high impedance high impedance high impedance rising edge 01 (30ms) output output output input 1 (after 30ms) input input output input
samurai adm6996lc/lcx/lhx 32 bits mode registers description data sheet 72 rev. 1.31, 2005-12-05 eesk, edi, edo(1) before this rising edge. adm6996lc/lcx/lhx will read this value into chip at point2. cpu must keep these values over point2. point2 is 200ns after reset rising edge. adm6996lc/lcx/lhx serial chips will read eeprom content at point4 which 800ns far away from the rising edge of reset. cpu must turn eeprom pins eecs, eesk, edi and edo to high-z or pull high before point4. if user want change state to high-z or pull high on eeprom pins, the order is cs-> di -> do -> sk is better. figure 10 cpu generated reset signal requirement a little bit different with the timing on writing eeprom. see below graph. must be careful when cs goes down after writing a command, sk must issue at least one clock. this is a difference between adm6996lc/lcx/lhx with eeprom write timing. if system without eeprom then user must write adm6996lc/lcx/lhx internal register by 93c66 timing. if user uses eeprom then the writing timing is depend on eeprom type. figure 11 cpu write eeprom command requirement 4.7 serial interface timing adm6996lc/lcx/lhx serial chip?s internal counter or eeprom access timing eesk: similar to the mdc signal. edi: similar to the mdio signal ecs: must keep be kept low. figure 12 serial interface read command timing preamble: at least 32 continuous 1 b ?s 200ns 800ns 200ns 100ms reset 12 3 45 cs sk write command z 0 ta register data [31:0] idle preamble tabl e sel ect 1 eeck eed i (sta) z 01000 0000 0 z z 0 11010 00 start opcode (read) device address 011111 register address eed i ( a d m6996)
data sheet 73 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 32 bits mode registers description start: 01 b (2 bits) opcode: 10 b (2 bits, only supports a read command) table select: 1 b = counter, 0 b = eeprom (1 bit) register address: read target register address. (7 bits) ta: turn around. register data: 32 bit data. counter output bit sequence is bit 31 to bit 0. if a user reads the eeprom then 32 bits of data will separate as two eeprom registers. the sequence is: 1. register +1, register (register is even number) 2. register, register-1(register is odd number) example: read register 00 h then the adm6996lc/lcx/lhx will drive 01 h & 00 h read register 03 h then adm6996lc/lcx/lhx will drive 03 h & 02 h idle: eesk must send at least one clock pulse at idle time adm6996lc/lcx/lhx issue reset internal counter command eesk: similar to the mdc signal edi: similar to the mdio signal ecs: must keep low. figure 13 serial interface reset command timing preamble: at least 32 continuous 1 b ?s start: 01 b (2 bits) opcode: 01 b (2 bits, reset command) device address: chip physical address as phyas[1:0]. reset_type: reset the counter by port number or by counter index 1 b = clear dedicate port?s all counters 0 b = clear dedicate counter port_number or counter index: user defines clear port or counter idle: eesk must send at least one clock pulse at idle time eeck eed i (sta) z 0 1011000 start opcode (reset) device address 00 0 0 01 port number or counter index preamble idle reset type
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 74 rev. 1.31, 2005-12-05 5 16 bits mode registers description broadcast storm adm6996lc/lcx/lhx allows users to limit the traffic of the broadcast address (da = ffffffffffff h ) to prevent them from blocking the switch bandwidth. if users also want to limit the multicast packets(da[40] = 1 b ), they can set the multicast packet counted into storming counter (see 0010 h , mp ) function. two threshold and storm enable bits (see 003b h and 003c h , storm_en , storm_100_th , storm_10_th ) are used to control the broadcast storm. the threshold is described in table 31 broadcast storming threshold . 1. time scale. adm6996lc/lcx/lhx uses 50ms as the scale to meter the storm packets. 2. storm keeps on at least 1.6 seconds if any of the ports meet the rising threshold in the 4 consecutive 50 ms intervals. in these 1.6 seconds, the ports meet the rising threshold and will start to discard the broadcast or multicast packets until the 50 ms interval expires. users could also disable input filter (see 000b h , if ) function to forward above packets to the un-congested port instead of discarding directly. 3. storm finishes. after the 1.6-second storm period, adm6996lc/lcx/lhx will check the port that makes the storm on. if all of these ports meet the falling threshold in the 2 consecutive 50 ms intervals and no other ports meet the rising threshold at the same time, adm6996lc/lcx/lhx will treat it the storm has finished. priority queue adm6996lc/lcx/lhx supports 4 priority queues and each is assigned a weight. user can see priority queue weight ratio for more detail. the eeprom provides adm6996lc/lcx/lhx with many option settings main settings ? port configuration: speed, duplex, flow control capability and tag/ untag. ? vlan & tos priority mapping ? broadcast storming rate and trunk. ? fiber select, auto mdix select ? vlan mapping ? per port buffer number ? priority queue and smart discard ratio table 31 broadcast storming threshold parameter rising threshold falling threshold all link ports are 100m 100m threshold (see 003b h ) 1/2 100m threshold not all link ports are 100m 10m threshold (see 003c h ) 1/2 10m threshold table 32 priority queue weight ratio queue weight queue 0 weight = 1 queue 1 weight = ?queue 1 weight? bits in 0025 h queue 2 weight = ?queue 2 weight? bits in 0026 h queue 3 weight = ?queue 3 weight? bits in 0027 h
data sheet 75 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description table 33 registers address space module base address end address note eeprom basic register map 0000 h 003f h eeprom extended register map 0040 h 009c h counter and switch status map 00a0 h 0143 h phy register map 0200 h 02ff h table 34 registers overview register short name register long name offset address page number sig signature register 00 h 85 p0bc p0 basic control register 01 h 85 res0 reserved register 0 02 h 87 p1 basic control register 1 03 h 86 res1 reserved register 1 04 h 87 p2 basic control register 2 05 h 86 res2 reserved register 2 06 h 87 p3 basic control register 3 07 h 86 p4 basic control register 4 08 h 87 p5 basic control register 5 09 h 87 sc0 system control register 0 0a h 88 sc1 system control register 1 0b h 89 res3 reserved register 3 0c h 87 res4 reserved register 4 0d h 87 vpm vlan priority map register 0e h 90 tpm tos priority map register 0f h 91 sc2 system control register 2 10 h 92 sc3 system control register 3 11 h 92 sc4 system control register 4 12 h 94 p0so port 0 security option 13 h 95 p1so port 1 security option 14 h 96 p2so port 2 security option 15 h 96 p3so port 3 security option 16 h 96 p4so port 4 security option 17 h 96 p5so port 5 security option 18 h 96 ufgpm unicast port map and forward group port map 19 h 96 bfgpm broadcast port map andforward group port map 1a h 97 mfgpm multicast port map and forward group port map 1b h 98 rfgpm reserve port map and forward group port map 1c h 98 piofgpm packet identification option, forward group port map 1d h 99
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 76 rev. 1.31, 2005-12-05 vpefgpm vlan priority enable and forward group port map 1e h 100 spefgpm service priority enable and forward group port map 1f h 101 ifntfgpm input force no tag and forward group port map 20 h 102 iffgpm ingress filter andforward group port map 21 h 103 vsdfgpm vlan security disable and forward group port map 22 h 104 res5 reserved register 5 23 h 87 res6 reserved register 6 24 h 87 imeijt igmp/mldtrap enable and input jam threshold register 25 h 105 q2wvecpo queue 2 weight, vid exist check, and pppoe port only 26 h 105 q3wbpvao queue 3 weight, back to port vlan, and admit only vlan-tagged 27 h 106 idtep input double tag enable, and p0vid[11:4] 28 h 106 odtep output double tag enable, and p1vid[11:4] 29 h 107 otbp output tag bypass, and p2vid[11:4] 2a h 107 p11_4 p3vid[11:4], and p4vid[11:4] 2b h 108 racp reserved address control, and p5vid[11:4] 2c h 108 phyc phy control register 2d h 108 atet adm tag ether type 2e h 109 pr phy restart register 2f h 109 misc miscellaneous register 30 h 110 bbc0 basic bandwidth control register 0 31 h 111 bbc1 basic bandwidth control register 1 32 h 111 bce bandwidth control enable register 33 h 112 ebc0 extended bandwidth control register 0 34 h 114 ebc1 extended bandwidth control register 1 35 h 114 ebc2 extended bandwidth control register 2 36 h 115 ebc3 extended bandwidth control register 3 37 h 115 ebc4 extended bandwidth control register 4 38 h 116 ebc5 extended bandwidth control register 5 39 h 117 dvmebc6 default vlan member and extended bandwidth control register 6 3a h 117 ns0 new storm register 0 3b h 118 ns1 new storm register 1 3c h 118 nrac0 new reserve address control register 0 3d h 119 nrac1 new reserve address control register 1 3e h 120 res7 reserved register 7 3f h 87 vf0l vlan filter 0 low 40 h 122 table 34 registers overview (cont?d) register short name register long name offset address page number
data sheet 77 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description vf0h vlan filter 0 high 41 h 123 vf1l vlan filter 1 low 42 h 122 vf1h vlan filter 1 high 43 h 123 vf2l vlan filter 2 low 44 h 122 vf2h vlan filter 2 high 45 h 123 vf3l vlan filter 3low 46 h 122 vf3h vlan filter 3 high 47 h 123 vf4l vlan filter 4 low 48 h 122 vf4h vlan filter 4 high 49 h 123 vf5l vlan filter 5 low 4a h 122 vf5h vlan filter 5 high 4b h 123 vf6l vlan filter 6 low 4c h 122 vf6h vlan filter 6 high 4d h 123 vf7l vlan filter 7 low 4e h 122 vf7h vlan filter 7 high 4f h 123 vf8l vlan filter 8 low 50 h 122 vf8h vlan filter 8 high 51 h 123 vf9l vlan filter 9 low 52 h 122 vf9h vlan filter 9 high 53 h 123 vf10l vlan filter 10 low 54 h 122 vf10h vlan filter 10 high 55 h 123 vf11l vlan filter 11 low 56 h 122 vf11h vlan filter 11 high 57 h 123 vf12l vlan filter 12 low 58 h 122 vf12h vlan filter 12 high 59 h 123 vf13l vlan filter 13 low 5a h 122 vf13h vlan filter 13 high 5b h 123 vf14l vlan filter 14 low 5c h 122 vf14h vlan filter 14 high 5d h 123 vf15l vlan filter 15 low 5e h 122 vf15h vlan filter 15 high 5f h 123 tf0 type filter 0 60 h 124 tf1 type filter 1 61 h 124 tf2 type filter 2 62 h 124 tf3 type filter 3 63 h 124 tf4 type filter 4 64 h 124 tf5 type filter 5 65 h 124 tf6 type filter 6 66 h 124 tf7 type filter 7 67 h 124 pf_1_0 protocol filter 1 and 0 68 h 124 pf_3_2 protocol filter 3 and 2 68 h 125 table 34 registers overview (cont?d) register short name register long name offset address page number
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 78 rev. 1.31, 2005-12-05 pf_5_4 protocol filter 5 and 4 69 h 125 pf_7_6 protocol filter 7 and 6 6a h 125 res8 reserved register 8 6c h 87 res9 reserved register 9 6d h 87 res10 reserved register 10 6e h 87 res11 reserved register 11 6f h 87 res12 reserved register 12 70 h 87 res13 reserved register 13 71 h 87 res14 reserved register 14 72 h 87 res15 reserved register 15 73 h 87 res16 reserved register 16 74 h 87 res17 reserved register 17 75 h 87 res18 reserved register 18 76 h 87 res19 reserved register 19 77 h 87 res20 reserved register 20 78 h 87 res21 reserved register 21 79 h 88 res22 reserved register 22 7a h 88 res23 reserved register 23 7b h 88 res24 reserved register 24 7c h 88 res25 reserved register 25 7d h 88 res26 reserved register 26 7e h 88 res27 reserved register 27 7f h 88 res28 reserved register 28 80 h 88 res29 reserved register 29 81 h 88 res30 reserved register 30 82 h 88 res31 reserved register 31 83 h 88 res32 reserved register 32 84 h 88 res33 reserved register 33 85 h 88 res34 reserved register 34 86 h 88 res35 reserved register 35 87 h 88 res36 reserved register 36 88 h 88 res37 reserved register 37 89 h 88 res38 reserved register 38 8a h 88 res39 reserved register 39 8b h 88 tuf0 tcp/udp filter 0 8c h 125 tuf1 tcp/udp filter 1 8d h 125 tuf2 tcp/udp filter 2 8e h 125 tuf3 tcp/udp filter 3 8f h 125 tuf4 tcp/udp filter 4 90 h 125 tuf5 tcp/udp filter 5 91 h 125 tuf6 tcp/udp filter 6 92 h 125 table 34 registers overview (cont?d) register short name register long name offset address page number
data sheet 79 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description tuf7 tcp/udp filter 7 93 h 125 tfa type filter action 94 h 126 pfa protocol filter action 95 h 126 tua0 tcp/udp action 0 96 h 127 tua1 tcp/udp action 1 97 h 128 tua2 tcp/udp action 2 98 h 129 res40 reserved register 40 99 h 88 ie interrupt enable register 9a h 130 is interrupt status register 9b h 130 res41 reserved register 41 9c h 88 ci0 chip identifier 0 a0 h 131 ci1 chip identifier 1 a1 h 131 ps0 port status 0 a2 h 132 ps1 port status 1 a3 h 133 ps2 port status 2 a4 h 134 res42 reserved register 42 a5 h 88 res43 reserved register 43 a6 h 88 res44 reserved register 44 a7 h 88 cl0 port 0 receive packet counter low a8 h 134 ch0 port 0 receive packet counter high a9 h 136 cl1 port 1 receive packet counter low ac h 135 ch1 port 1 receive packet counter high ad h 136 cl2 port 2 receive packet counter low b0 h 135 ch2 port 2 receive packet counter high b1 h 136 cl3 port 3 receive packet counter low b4 h 135 ch3 port 3 receive packet counter high b5 h 136 cl4 port 4 receive packet counter low b6 h 135 ch4 port 4 receive packet counter high b7 h 136 cl5 port 5 receive packet counter low b8 h 135 ch5 port 5 receive packet counter high b9 h 136 cl6 port 0 receive packet byte count low ba h 135 ch6 port 0 receive packet byte count high bb h 136 cl7 port 1 receive packet byte count low be h 135 ch7 port 1 receive packet byte count high bf h 136 cl8 port 2 receive packet byte count low c2 h 135 ch8 port 2 receive packet byte count high c3 h 136 cl9 port 3 receive packet byte count low c6 h 135 ch9 port 3 receive packet byte count high c7 h 136 cl10 port 4 receive packet byte count low c8 h 135 ch10 port 4 receive packet byte count high c9 h 136 cl11 port 5 receive packet byte count low ca h 135 table 34 registers overview (cont?d) register short name register long name offset address page number
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 80 rev. 1.31, 2005-12-05 ch11 port 5 receive packet byte count high cb h 136 cl12 port 0 transmit packet count low cc h 135 ch12 port 0 transmit packet count high cd h 136 cl13 port 1 transmit packet count low d0 h 135 ch13 port 1 transmit packet count high d1 h 136 cl14 port 2 transmit packet count low d4 h 135 ch14 port 2 transmit packet count high d5 h 136 cl15 port 3 transmit packet count low d8 h 135 ch15 port 3 transmit packet count high d9 h 137 cl16 port 4 transmit packet count low da h 135 ch16 port 4 transmit packet count high db h 137 cl17 port 5 transmit packet count low dc h 135 ch17 port 5 transmit packet count high dd h 137 cl18 port 0 transmit packet byte count low de h 135 ch18 port 0 transmit packet byte count high df h 137 cl19 port 1 transmit packet byte count low e2 h 135 ch19 port 1 transmit packet byte count high e3 h 137 cl20 port 2 transmit packet byte count low e6 h 135 ch20 port 2 transmit packet byte count high e7 h 137 cl21 port 3 transmit packet byte count low ea h 135 ch21 port 3 transmit packet byte count high eb h 137 cl22 port 4 transmit packet byte count low ec h 135 ch22 port 4 transmit packet byte count high ed h 137 cl23 port 5 transmit packet byte count low ee h 135 ch23 port 5 transmit packet byte count high ef h 137 cl24 port 0 collision count low f0 h 135 ch24 port 0 collision count high f1 h 137 cl25 port 1 collision count low f4 h 135 ch25 port 1 collision count high f5 h 137 cl26 port 2 collision count low f8 h 135 ch26 port 2 collision count high f9 h 137 cl27 port 3 collision count low fc h 135 ch27 port 3 collision count high fd h 137 cl28 port 4 collision count low fe h 135 ch28 port 4 collision count high ff h 137 cl29 port 5 collision count low 100 h 135 ch29 port 5 collision count high 101 h 137 cl30 port 0 error count low 102 h 136 ch30 port 0 error count high 103 h 137 cl31 port 1 error count low 106 h 136 ch31 port 1 error count high 107 h 137 table 34 registers overview (cont?d) register short name register long name offset address page number
data sheet 81 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description cl32 port 2 error count low 10a h 136 ch32 port 2 error count high 10b h 137 cl33 port 3 error count low 10e h 136 ch33 port 3 error count high 10f h 137 cl34 port 4 error count low 110 h 136 ch34 port 4 error count high 111 h 137 cl35 port 5 error count low 112 h 136 ch35 port 5 error count high 113 h 137 off0 over-flow flag 0 114 h 137 off1 over-flow flag 1 115 h 138 off2 over-flow flag 2 116 h 139 off3 over-flow flag 3 117 h 140 off4 over-flow flag 4 118 h 140 off5 over-flow flag 5 119 h 141 hsl hardware setting low register 130 h 142 hsh hardware setting high register 131 h 142 res45 reserved register 45 132 h 88 res46 reserved register 46 133 h 88 res47 reserved register 47 134 h 88 ao assign option register 135 h 143 res48 reserved register 48 136 h 88 res49 reserved register 49 137 h 88 svp security violation port 138 h 144 ss0 security status 0 139 h 144 ss1 security status 1 13a h 145 flas first lock address search 13b h 145 fla1 first lock address [15:0] 13c h 146 fla2 first lock address [31:16] 13d h 146 fla3 first lock address [47:32] 13e h 146 flf first lock fid 13f h 147 ccl counter control low register 140 h 147 res50 reserved register 50 141 h 88 csl counter status low register 142 h 148 csh counter status high register 143 h 148 phy_c0 phy control register of port 0 200 h 148 phy_s0 phy status register of port 0 201 h 151 phy_i0_a phy identifier register of port 0 (a) 202 h 152 phy_i0_b phy identifier register of port 0 (b) 203 h 153 anap0 auto negotiation advertisement register of port 0 204 h 154 anlpa0 auto negotiation link partner ability register of port 0 205 h 155 table 34 registers overview (cont?d) register short name register long name offset address page number
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 82 rev. 1.31, 2005-12-05 ane0 auto negotiation expansion register of port 0 206 h 156 npt0 next page transmit register of port 0 207 h 157 lpnp0 link partner next page register of port 0 208 h 158 phy_c1 phy control register of port 1 220 h 150 phy_s1 phy status register of port 1 221 h 152 phy_i1_a phy identifier register of port 1 (a) 222 h 153 phy_i1_b phy identifier register of port 1 (b) 223 h 153 anap1 auto negotiation advertisement register of port 1 224 h 155 anlpa1 auto negotiation link partner ability register of port 1 225 h 156 ane1 auto negotiation expansion register of port 1 226 h 157 npt1 next page transmit register of port 1 227 h 158 lpnp1 link partner next page register of port 1 228 h 159 phy_c2 phy control register of port 2 240 h 150 phy_s2 phy status register of port 2 241 h 152 phy_i2_a phy identifier register of port 2 (a) 242 h 153 phy_i2_b phy identifier register of port 2 (b) 243 h 153 anap2 auto negotiation advertisement register of port 2 244 h 155 anlpa2 auto negotiation link partner ability register of port 2 245 h 156 ane2 auto negotiation expansion register of port 2 246 h 157 npt2 next page transmit register of port 2 247 h 158 lpnp2 link partner next page register of port 2 248 h 159 phy_c3 phy control register of port 3 260 h 150 phy_s3 phy status register of port 3 261 h 152 phy_i3_a phy identifier register of port 3 (a) 262 h 153 phy_i3_b phy identifier register of port 3 (b) 263 h 154 anap3 auto negotiation advertisement register of port 3 264 h 155 anlpa3 auto negotiation link partner ability register of port 3 265 h 156 ane3 auto negotiation expansion register of port 3 266 h 157 npt3 next page transmit register of port 3 267 h 158 lpnp3 link partner next page register of port 3 268 h 159 phy_c4 phy control register of port 4 280 h 150 phy_s4 phy status register of port 4 281 h 152 phy_i4_a phy identifier register of port 4 (a) 282 h 153 phy_i4_b phy identifier register of port 4 (b) 283 h 154 anap4 auto negotiation advertisement register of port 4 284 h 155 anlpa4 auto negotiation link partner ability register of port 4 285 h 156 ane4 auto negotiation expansion register of port 4 286 h 157 table 34 registers overview (cont?d) register short name register long name offset address page number
data sheet 83 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description the register is addressed wordwise. npt4 next page transmit register of port 4 287 h 158 lpnp4 link partner next page register of port 4 288 h 159 table 35 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interrupt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be cleared due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 34 registers overview (cont?d) register short name register long name offset address page number
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 84 rev. 1.31, 2005-12-05 table 36 registers clock domains clock short name description ??
data sheet 85 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description 5.1 eeprom basic registers signature register p0 basic control register sig offset reset value signature register 00 h 4154 h field bits type description sig 15:0 ro signature the value must be 4154 h . adm6996lc/lcx/lhx uses this value to check if the eeprom is attached. if the value in the eeprom does not equal to 4154 h , adm6996lc/lcx/lhx will stop loading the eeprom even if the eeprom is attached. adm6996lc/lcx/lhx will use the default value to initialize. p0bc offset reset value p0 basic control register 01 h 040f h field bits type description res 15 rw reserved selfx_ee 14 rw select fx this bit is used together with the value (p4fx_hw) on the pin p4fx during the power on reset to decide if the phy operates on the fiber mode. this bit is useless in port 5. port 0, 1, 2, 3: selfx_ee description port 4: {p4fx_hw, selfx_ee} description 1x b port 4: port 4 will operate in the fiber mode 00 b port 4: port 4 will operate in the twisted mode 01 b port 4: port 4 will operate in the fiber mode ur 6,* uz 5hv uz 6(/) ;b(( uz 39,'b uz 33 uz 33( uz ,39/ $1 uz 3' uz 237( uz '$ uz 6$ uz $1( uz )&(
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 86 rev. 1.31, 2005-12-05 similar registers pvid3_0 13:10 rw private vid see 0028 h ~ 002c h to find the other pvid [11:4] pp 9:8 rw port priority 00 b assign packets to queue 0 01 b assign packets to queue 1 10 b assign packets to queue 2 11 b assign packets to queue 3 ppe 7 rw port priority enable 0 b the port priority is disabled 1 b the port priority is enabled ipvlan 6 rw ip over vlan pri 0 b use the priority bits in the tag header to assign the priority queue 1 b use the ip pri to assign the priority queue pd 5 rw port disable 0 b port 0, 1, 2, 3, 4: phy work s normally. port 5: port 5 works normally 1 b port 0, 1, 2, 3, 4. phy is disabled. port 5: port 5 is forced to link down opte 4 rw output packet tagging enable 0 b untagged packets are transmitted 1 b tagged packets are transmitted da 3 rw duplex ability it is useless in port 5. 0 b recommend phy to work in the half duplex mode 1 b recommend phy to work in the full duplex mode sa 2 rw speed ability 0 b recommend phy to work in the 10m mode 1 b recommend phy to work in the 100m mode ane 1 rw auto negotiation enable 0 b recommend phy to work without auto negotiation 1 b recommend phy to work with auto negotiation, when the value on the pin dupcol0 during the power on reset is 1 fce 0 rw flow control enable 0 b recommend mac to work without pause or back pressure 1 b in full duplex, recommend mac to work with pause when the value on the txd0 during the power on reset is 1. in half duplex, recommend mac to work with back pressure when the value on the dupcol2 during the power on reset is 1 table 37 basic control registers 1 to 5 register short name register long name offset address page number p1 basic control register 1 03 h p2 basic control register 2 05 h p3 basic control register 3 07 h field bits type description
data sheet 87 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description reserved register 0 similar registers p4 basic control register 4 08 h p5 basic control register 5 09 h res0 offset reset value reserved register 0 02 h 0000 h field bits type description res 15:0 r reserved table 38 reserved registers register short name register long name offset address page number res1 reserved register 1 04 h res2 reserved register 2 06 h res3 reserved register 3 0c h res4 reserved register 4 0d h res5 reserved register 5 23 h res6 reserved register 6 24 h res7 reserved register 7 3f h res8 reserved register 8 6c h res9 reserved register 9 6d h res10 reserved register 10 6e h res11 reserved register 11 6f h res12 reserved register 12 70 h res13 reserved register 13 71 h res14 reserved register 14 72 h res15 reserved register 15 73 h res16 reserved register 16 74 h res17 reserved register 17 75 h res18 reserved register 18 76 h res19 reserved register 19 77 h res20 reserved register 20 78 h table 37 basic control registers 1 to 5 (cont?d) register short name register long name offset address page number u 5hv
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 88 rev. 1.31, 2005-12-05 system control register 0 res21 reserved register 21 79 h res22 reserved register 22 7a h res23 reserved register 23 7b h res24 reserved register 24 7c h res25 reserved register 25 7d h res26 reserved register 26 7e h res27 reserved register 27 7f h res28 reserved register 28 80 h res29 reserved register 29 81 h res30 reserved register 30 82 h res31 reserved register 31 83 h res32 reserved register 32 84 h res33 reserved register 33 85 h res34 reserved register 34 86 h res35 reserved register 35 87 h res36 reserved register 36 88 h res37 reserved register 37 89 h res38 reserved register 38 8a h res39 reserved register 39 8b h res40 reserved register 40 99 h res41 reserved register 41 9c h res42 reserved register 42 a5 h res43 reserved register 43 a6 h res44 reserved register 44 a7 h res45 reserved register 45 132 h res46 reserved register 46 133 h res47 reserved register 47 134 h res48 reserved register 48 136 h res49 reserved register 49 137 h res50 reserved register 50 141 h sc0 offset reset value system control register 0 0a h 5902 h table 38 reserved registers (cont?d) register short name register long name offset address page number uz (5&037+ uz 5hv uz 3&( uz 59,' uz 5hv uz 59,' ))) uz '),' uz 5hv
data sheet 89 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description system control register 1 field bits type description ercmpth 15:12 rw earlier cycles for transmission it means the earlier cycles for transmission used in adm6996lc/lcx/lhx. it is for the engineer debug purpose. res 11 rw reserved pce 10 rw priority change enable 0 b do not change the priority in the tag header 1 b change the priority field in the tag header rvid 9 rw replace vid0 and vid1 0 b do not replace 1 b replace res 8 rw reserved rvidfff 7 rw replace vidfff always drop dfid 6:3 rw default fid always 0000 b res 2:0 rw reserved sc1 offset reset value system control register 1 0b h 8001 h field bits type description dfefd 15 rw disable far-end-fault detection 0 b far-end-fault detect ion is enabled 1 b far-end-fault detect ion is disabled if 14 rw input filter 0 b discard packets directly when storming or the lack of input buffers 1 b forward packets to the un-congested port when storming or the lack of input buffers res 13:9 rw reserved cms 8 rw carrier mask select 0 b mask crs of 4 cycles 1 b mask crs of 5 cycles te 7 rw port 3 and port 4 trunk enable 0 b no trunk is enabled 1 b port 3 and port 4 are trunked uz ')() ' uz ,) uz 5hv uz &06 uz 7( uz 76,( uz 5hv uz 1(
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 90 rev. 1.31, 2005-12-05 vlan priority map register tsie 6 rw transmit short ipg enable 0 b 96 bits time is used 1 b 88/96 bits time is used res 5:1 rw reserved ne 0 rw new eeprom 0 b use old eeprom functions 1 b new eeprom function is enabled vpm offset reset value vlan priority map register 0e h fa50 h field bits type description pq7 15:14 rw priority queue 7 these 2 bits are used as the priority queue when the tagged packets with the user priority = 111 b are received on the port. 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 pq6 13:12 rw priority queue 6 these 2 bits are used as the priority queue when the tagged packets with the user priority = 110 b are received on the port. pq5 11:10 rw priority queue 5 these 2 bits are used as the priority queue when the tagged packets with the user priority = 101 b are received on the port. pq4 9:8 rw priority queue 4 these 2 bits are used as the priority queue when the tagged packets with the user priority = 100 b are received on the port. pq3 7:6 rw priority queue 3 these 2 bits are used as the priority queue when the tagged packets with the user priority = 011 b are received on the port. pq2 5:4 rw priority queue 2 these 2 bits are used as the priority queue when the tagged packets with the user priority = 010 b are received on the port. pq1 3:2 rw priority queue 1 these 2 bits are used as the priority queue when the tagged packets with the user priority = 001 b are received on the port. field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
data sheet 91 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description tos priority map register pq0 1:0 rw priority queue 0 these 2 bits are used as the priority queue when the tagged packets with the user priority = 000 b are received on the port. tpm offset reset value tos priority map register 0f h fa50 h field bits type description pq7 15:14 rw priority queue 7 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 111 b 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 pq6 13:12 rw priority queue 6 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 110 b pq5 11:10 rw priority queue 5 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 101 b pq4 9:8 rw priority queue 4 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 100 b pq3 7:6 rw priority queue 3 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 011 b pq2 5:4 rw priority queue 2 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 010 b pq1 3:2 rw priority queue 1 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 001 b pq0 1:0 rw priority queue 0 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 000 b field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 92 rev. 1.31, 2005-12-05 system control register 2 system control register 3 sc2 offset reset value system control register 2 10 h 0040 h field bits type description res 15:8 rw reserved ad 7 rw aging disable useless in adm6996lc/lcx/lhx 0 b age enable 1 b age disable cc 6 rw rx clock change to tx clock for gpsi interface 0 b adm6996lc/lcx/lhx does not use tx clock to replace rx clock when rx clock stops. 1 b adm6996lc/lcx/lhx uses tx clock to replace rx clock when rx clock stops mp 5 rw multicast packet counted into the storm counter 0 b only broadcast packets are counted into the storming counter 1 b multicast and broadcast packets are counted into the storming counter ccd 4 rw crc check disable 0 b check crc 1 b do not check crc bd 3 rw back off disable 0 b back-off is enabled 1 b back-off is disabled se 2 rw storming enable it is used in adm6996l/f style storm control. 0 b disable broadcast/multicast storm protection. 1 b enable boradcast/multicast storm protection. st 1:0 rw storming threshold[1:0] it is used in adm6996l/f style storm control. sc3 offset reset value system control register 3 11 h e300 h uz 5hv uz $' uz && uz 03 uz &&' uz %' uz 6( uz 67
data sheet 93 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description field bits type description cpn 15:13 rw cpu port number 000 b the cpu is attached to port 0 001 b the cpu is attached to port 1 010 b the cpu is attached to port 2 011 b the cpu is attached to port 3 100 b the cpu is attached to port 4 101 b the cpu is attached to port 5 111 b no cpu exists res 12:11 rw reserved p10rw pause also add s speci a l tag when special tag transmit is enabled . 0 b do not add special tag on the pause packets 1 b add special tag in the pause packets mpl 9:7 rw max packet length 000 b 1518 bytes 001 b 1536 bytes 010 b 1664 bytes 110 b 1522 bytes x11 b 1784 bytes 10x b 1784 bytes nse 6 rw new storming enable 0 b use the adm6996l/f style storming control 1 b use the adm6996lc/lcx/lhx style storming control tbv 5 rw tag base vlan 0 b port vlan 1 b tagged vlan mce 4 rw mac clone enable 0 b mac clone is disabled 1 b mac clone is enabled qo 3 rw queue option it ? s the test for the designer in the queue control. ipi 2 rw interrupt polarity inverter 0 b the interrupt signal is active pull low 1 b the interrupt signal is active pull high ats 1:0 rw aging timer select 00 b 300 seconds 01 b 75 seconds 10 b 18 seconds 11 b 1 second uz &31 uz 5hv uz 3 uz 03/ uz 16( uz 7%9 uz 0&( uz 42 uz ,3, uz $76
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 94 rev. 1.31, 2005-12-05 system control register 4 sc4 offset reset value system control register 4 12 h 3600 h field bits type description dp 15 rw drop packet when excessive collision happen 0 b do not drop 1 b drop dcs 14 rw duplex and col separate 0 b indicate the duplex and collision status at the same time 1 b indicate the duplex status only res 13:12 rw reserved tle 11 rw ten limit enable this function works only when full flow control/half back pressure is enabled. 0 b the switch will not ignore 10 mbit/s paths even when the ten limit reaches 1 b the switch will forward packets with multicast, broadcast, or unicast but not learned da addresses from 100 mbit/s only to 100 mbit/s ports and ignore the 10m paths when the ten limit reaches. this function allows the switch to balance the high and the low speed res 10:9 rw reserved o5fl 8 rw old p5 first lock 0 b first lock is disabled 1 b first lock is enabled o4fl 7 rw old p4 first lock 0 b first lock is disabled 1 b first lock is enabled o3fl 6 rw old p3 first lock 0 b first lock is disabled 1 b first lock is enabled pi 5 rw pause ignore 0 b do not ignore pause packets 1 b ignore pause packets in half duplex or in full duplex when flow control is not enabled o2fl 4 rw old p2 first lock 0 b first lock is disabled 1 b first lock is enabled uz '3 uz '&6 uz 5hv uz 7/( uz 5hv uz 2)/ uz 2)/ uz 2)/ uz 3, uz 2)/ uz '8$/ b&2 uz 2)/ uz /('b (1$ uz 2)/
data sheet 95 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description port 0 security option port spanning tree state and forward group port map. dual_colo r_ee 3rw dual color in mdc / mdio with cpu see chapter 3.23 led display for more detail information. 0 b single color 1 b dual color o1fl 2 rw old p1 first lock 0 b first lock is disabled 1 b first lock is enabled led_enable 1 rw led enable 0 b disable 1 b enable o0fl 0 rw old p0 first lock 0 b first lock is disabled 1 b first lock is enabled p0so offset reset value port 0 security option 13 h 01d5 h field bits type description res 15:9 r reserved p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved field bits type description u 5hv uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 96 rev. 1.31, 2005-12-05 similar registers unicast port map andforward group port map p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member table 39 pxso registers register short name register long name offset address page number p1so port 1 security option 14 h p2so port 2 security option 15 h p3so port 3 security option 16 h p4so port 4 security option 17 h p5so port 5 security option 18 h ufgpm offset reset value unicast port map andforward group port map 19 h ffd5 h field bits type description res 15 r reserved up 14:9 rw unicast portmap see chapter 3.15.2 packet forwarding for more detail information. p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved field bits type description u 5hv uz 83 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 97 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description broadcast port map andforward group port map p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member bfgpm offset reset value broadcast port map andforward group port map 1a h ffd5 h field bits type description res 15 r reserved bp 14:9 rw broadcast portmap always 111111 b p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved field bits type description u 5hv uz %3 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 98 rev. 1.31, 2005-12-05 multicast port map and forward group port map reserve port map and forward group port map p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member mfgpm offset reset value multicast port map and forward group port map 1b h ffd5 h field bits type description res 15 r reserved mp 14:9 rw multicast portmap always 111111 b p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member field bits type description u 5hv uz 03 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 99 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description packet identification option, forward group port map rfgpm offset reset value reserve port map and forward group port map 1c h ffd5 h field bits type description res 15 r reserved rp 14:9 rw reserve portmap always 111111 b p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member piofgpm offset reset value packet identification option, forward group port map 1d h ffd5 h u 5hv uz 53 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 100 rev. 1.31, 2005-12-05 vlan priority enable and forward group port map field bits type description res 15 rw reserved divs 14 rw do not identify vlan after snap 0 b identify 1 b do not identify dii6p 13 rw do not identify ipv6 in pppoe 0 b identify 1 b do not identify res 12:11 rw reserved diip 10 rw do not identify ip in pppoe 0 b identify 1 b do not identify res 9 rw reserved p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member uz 5hv uz ',96 uz ',, 3 uz 5hv uz ',,3 uz 5hv uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 101 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description service priority enable and forward group port map vpefgpm offset reset value vlan priority enable and forward group port map 1e h ffd5 h field bits type description res 15 r reserved vpe 14:9 rw vlan priority enable 0 b do not care the pri in the tag header 1 b pri in the tag header will be taken into priority determination consideration p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a membe res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member spefgpm offset reset value service priority enable and forward group port map 1f h ffd5 h u 5hv uz 93( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 102 rev. 1.31, 2005-12-05 input force no tag and forward group port map? field bits type description res 15 r reserved spe 14:9 rw service priority enable 0 b don?t care ipv4 tos /ipv6 traffic class 1 b care ipv4 tos/ipv6 traffic for priority decision p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member ifntfgpm offset reset value input force no tag and forward group port map 20 h ffd5 h u 5hv uz 63( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz ,)17( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 103 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description ingress filter andforward group port map field bits type description res 15 r reserved ifnte 14:9 rw input force no tag enable 0 b disabled 1 b enabled p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member iffgpm offset reset value ingress filter andforward group port map 21 h ffd5 h field bits type description res 15 r reserved ife 14:9 rw ingress filter enable always 111111 b u 5hv uz ,)( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 104 rev. 1.31, 2005-12-05 vlan security disable and forward group port map p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member vsdfgpm offset reset value vlan security disable and forward group port map 22 h ffd5 h field bits type description res 15 r reserved vsd 14:9 rw vlan security disable always 111111 b p5 8 rw port 5 is a member of the forwarding group 0 b port 5 is not a member 1 b port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b port 4 is not a member 1 b port 4 is a member field bits type description u 5hv uz 96' uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 105 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description igmp/mldtrap enable and input jam threshold register queue 2 weight, vid exist check, and pppoe port only p3 6 rw port 3 is a member of the forwarding group 0 b port 3 is not a member 1 b port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b port 2 is not a member 1 b port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b port 1 is not a member 1 b port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b port 0 is not a member 1 b port 0 is a member imeijt offset reset value igmp/mldtrap enable and input jam threshold register 25 h 1000 h field bits type description q1w 15:12 rw queue 1 weight see table 32 priority queue weight ratio for more detail information. res 11:6 rw reserved ijt 5:0 rw input jam threshold q2wvecpo offset reset value queue 2 weight, vid exist check, and pppoe port only 26 h 1000 h field bits type description uz 4: uz 5hv uz ,-7
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 106 rev. 1.31, 2005-12-05 queue 3 weight, back to port vlan, and admit only vlan-tagged input double tag enable, and p0vid[11:4] field bits type description q2w 15:12 rw queue 2 weight see table 32 for more detail information. vc 11:6 rw vid check always 000000 b res 5:0 rw reserved q3wbpvao offset reset value queue 3 weight, back to port vlan, and admit only vlan-tagged 27 h 1000 h field bits type description q3w 15:12 rw queue 3 weight see table 32 for more detail information. bpv 11:6 rw back to port vlan always 000000 b aovtp 5:0 rw admit only vlan_tagged packet always 000000 b idtep offset reset value input double tag enable, and p0vid[11:4] 28 h 0000 h uz 4: uz 9& uz 5hv uz 4: uz %39 uz $2973 uz 5hv uz ,'7( uz 39,'bb
data sheet 107 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description output double tag enable, and p1vid[11:4] output tag bypass, and p2vid[11:4] field bits type description res 15:14 rw reserved idte 13:8 rw input double tag enable the register is reserved for internal use only and should be kept 0b p0vid_11_4 7:0 rw p0vid[11:4] vid bit 11 ~ 4 fo port 0 odtep offset reset value output double tag enable, and p1vid[11:4] 29 h 0000 h field bits type description res 15:8 rw reserved p1vid_11_4 7:0 rw p1vid[11:4] vid bit 11 ~ 4 of port 1. otbp offset reset value output tag bypass, and p2vid[11:4] 2a h 3f00 h field bits type description res 15:14 rw reserved otbe 13:8 rw output tag bypass enable always 000000 b p2vid_11_4 7:0 rw p2vid[11:4] vid bit 11 ~ 4 of port 2. uz 5hv uz 39,'bb uz 5hv uz 27%( uz 39,'bb
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 108 rev. 1.31, 2005-12-05 p3vid[11:4], and p4vid[11:4] reserved address control, and p5vid[11:4] phy control register p11_4 offset reset value p3vid[11:4], and p4vid[11:4] 2b h 0000 h field bits type description p4vid_11_4 15:8 rw p4vid[11:4] vid bit 11 ~ 4 of port 4. p3vid_11_4 7:0 rw p3vid[11:4] vid bit 11 ~ 4 of port 3. racp offset reset value reserved address control, and p5vid[11:4] 2c h d000 h field bits type description ama3 15 rw action of mac address 3 the action of mac address = 0180c2000010 h ~ 0180c20000ff h ama2 14 rw action of mac address 2 the action of mac address = 0180c2000002 h ~ 0180c200000f h ama1 13 rw action of mac address 1 the action of mac address = 0180c2000001 h ama0 12 rw action of mac address 0 the action of mac address = 0180c2000000 h tag_shift 11:8 rw tag shift p5vid_11_4 7:0 rw p5vid[11:4] vid bit 11 ~ 4 of port 5 uz 39,'bb uz 39,'bb uz $0$ uz $0$ uz $0$ uz $0$ uz 7$*b6+,)7 uz 39,'bb
data sheet 109 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description adm tag ether type phy restart register phyc offset reset value phy control register 2d h 4442 h field bits type description cicd 15 rw chip id check disable 0 b check chip id in 32 bit sdc/sdo 1 b do not check chip id in 32 bit sdc/sdio res 14:0 rw reserved atet offset reset value adm tag ether type 2e h 0000 h field bits type description atet 15:0 rw adm tag ether type this value is used by the user to define their ether-type. when special tag receive is enabled, adm6996lc/lcx/lhx checks the packets on the cpu port to see if the two bytes following the sa are the same as adm tag ether type . if they are different, adm6996lc/lcx/lhx bypasses the special tag. if the same, adm6996lc/lcx/lhx will use the value in the special tag to do switching decisions . pr offset reset value phy restart register 2f h 0000 h uz &,&' uz 5hv uz $7(7
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 110 rev. 1.31, 2005-12-05 miscellaneous register field bits type description restart 15:0 rw restart adm6996lc/lcx/lhx writes this register to restart all the phys in the switch. the value written is not important. misc offset reset value miscellaneous register 30 h 0987 h field bits type description res 15:13 rw reserved p4 12 rw port 4 led mode 0 b linkact/dupcol/speed. 1 b link/act/speed. res 11:10 rw reserved dhcol 9 rw dual speed hub col_led enable 0 b normal led display. 1 b dual speed hub led display. port0 col led: 10m col led. port1 col led: 100m col led. dp 8 rw drop packets drop packets when the link partner does not follow the pause protocol. 0 b disable. 1 b enable to drop packets. b7rw bypass bypass tag/untag function. 0 b disable. 1 b enable to bypass tag/untag function res 6 rw reserved mceb 5 rw mac clone enable bits select 0 b select 1 bit mac clone function. 1 b select 2 bits mac clone function. res 4:0 rw reserved uz 5(67$57 uz 5hv uz 3 uz 5hv uz '+&2 / uz '3 uz % uz 5hv uz 0&(% uz 5hv
data sheet 111 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description basic bandwidth control register 0 basic bandwidth control register 1 bbc0 offset reset value basic bandwidth control register 0 31 h 0000 h field bits type description r3bw_th1 15 rw port 3 receive bandwidth maximum[3]. see register 0033 h , p3rbce for more detail. r3bw_th0 14:12 rw port 3 receive bandwidth configuration see register 0033 h , p3rbce for more detail. r2bw_th1 11 rw port 2 receive bandwidth maximum[3]. see register 0033 h , p2rbce for more detail. r2bw_th0 10:8 rw port 2 receive bandwidth configuration see register 0033 h , p2rbce for more detail. r1bw_th1 7 rw port 1 receive bandwidth maximum[3]. see register 0033 h , p1rbce for more detail. r1bw_th0 6:4 rw port 1 receive bandwidth configuration see register 0033 h , p1rbce for more detail. r0bw_th1 3 rw port 0 receive bandwidth maximum[3]. see register 0033 h , p0rbce for more detail. r0bw_th0 2:0 rw port 0 receive bandwidth configuration see register 0033 h , p0rbce for more detail. bbc1 offset reset value basic bandwidth control register 1 32 h 0000 h field bits type description t1bw_th1 15 rw port 1 transmit bandwidth maximum[3]. see register 0033 h , p1tbce for more detail. uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 112 rev. 1.31, 2005-12-05 bandwidth control enable register t1bw_th0 14:12 rw port 1 transmit bandwidth maximum[2:0]. see register 0033 h , p1tbce for more detail. t0bw_th1 11 rw port 0 transmit bandwidth maximum[3]. see register 0033 h , p0tbce for more detail. t0bw_th0 10:8 rw port 0 transmit bandwidth maximum[2:0]. see register 0033 h , p0tbce for more detail. r5bw_th1 7 rw port 5 receive bandwidth maximum[3]. see register 0033 h , p5rbce for more detail. r5bw_th0 6:4 rw port 5 receive bandwidth configuration see register 0033 h , p5rbce for more detail. r4bw_th1 3 rw port 4 receive bandwidth maximum[3]. see register 0033 h , p4rbce for more detail. r4bw_th0 2:0 rw port 4 receive bandwidth configuration see register 0033 h , p4rbce for more detail. bce offset reset value bandwidth control enable register 33 h 0000 h field bits type description ipcp 15 rw invert p4 clock in pcs 0 d disable 1 d enable clc 14 rw check the length of crs 0 d enable 1 d disable res 13 rw reserved anbce 12 rw adm6996lc/lcx/lhx new bandwidth control enable 0 b disable 1 b enable p5tbce 11 rw port 5 transmit bandwidth control enable the transmit bandwidth is { t5bw_th3 , t5bw_th2 , t5bw_th1 , t5bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable field bits type description uz ,3&3 uz &/& uz 5hv uz $1%& ( uz 37% &( uz 37% &( uz 37% &( uz 35% &( uz 35% &( uz 35% &( uz 37% &( uz 35% &( uz 37% &( uz 35% &( uz 37% &( uz 35% &(
data sheet 113 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description p4tbce 10 rw port 4 transmit bandwidth control enable the transmit bandwidth is { t4bw_th3 , t4bw_th2 , t4bw_th1 , t4bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p3tbce 9 rw port 3 transmit bandwidth control enable the transmit bandwidth is { t3bw_th3 , t3bw_th2 , t3bw_th1 , t3bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p5rbce 8 rw port 5 receive bandwidth control enable the receive bandwidth is { r5bw_th3 , r5bw_th2 , r5bw_th1 , r5bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p4rbce 7 rw port 4 receive bandwidth control enable the receive bandwidth is { r4bw_th3 , r4bw_th2 , r4bw_th1 , r4bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p3rbce 6 rw port 3 receive bandwidth control enable the receive bandwidth is { r3bw_th3 , r3bw_th2 , r3bw_th1 , r3bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p2tbce 5 rw port 2 transmit bandwidth control enable the transmit bandwidth is { t2bw_th3 , t2bw_th2 , t2bw_th1 , t2bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p2rbce 4 rw port 2 receive bandwidth control enable the receive bandwidth is { r2bw_th3 , r2bw_th2 , r2bw_th1 , r2bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p1tbce 3 rw port 1 transmit bandwidth control enable the transmit bandwidth is { t1bw_th3 , t1bw_th2 , t1bw_th1 , t1bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p1rbce 2 rw port 1 receive bandwidth control enable the receive bandwidth is { r1bw_th3 , r1bw_th2 , r1bw_th1 , r1bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable field bits type description
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 114 rev. 1.31, 2005-12-05 extended bandwidth control register 0 extended bandwidth control register 1 p0tbce 1 rw port 0 transmit bandwidth control enable the transmit bandwidth is { t0bw_th3 , t0bw_th2 , t0bw_th1 , t0bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable p0rbce 0 rw port 0 receive bandwidth control enable the receive bandwidth is { r0bw_th3 , r0bw_th2 , r0bw_th1 , r0bw_th0 , 000000 b } kbit/s. k = 1000. 0 b disable 1 b enable ebc0 offset reset value extended bandwidth control register 0 34 h 0000 h field bits type description t5bw_th1 15 rw port 5 transmit bandwidth maximum[3]. see register 0033 h , p5tbce for more detail. t5bw_th0 14:12 rw port 5 transmit bandwidth maximum[2:0]. see register 0033 h , p5tbce for more detail. t4bw_th1 11 rw port 4 transmit bandwidth maximum[3]. see register 0033 h , p4tbce for more detail. t4bw_th0 10:8 rw port 4 transmit bandwidth maximum[2:0]. see register 0033 h , p4tbce for more detail. t3bw_th1 7 rw port 3 transmit bandwidth maximum[3]. see register 0033 h , p3tbce for more detail. t3bw_th0 6:4 rw port 3 transmit bandwidth maximum[2:0]. see register 0033 h , p3tbce for more detail. t2bw_th1 3 rw port 2 transmit bandwidth maximum[3]. see register 0033 h , p2tbce for more detail. t2bw_th0 2:0 rw port 2 transmit bandwidth maximum[2:0]. see register 0033 h , p2tbce for more detail. field bits type description uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+
data sheet 115 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description extended bandwidth control register 2 extended bandwidth control register 3 ebc1 offset reset value extended bandwidth control register 1 35 h 0000 h field bits type description r3bw_th2 15:12 rw port 3 receive bandwidth maximum[7:4]. see register 0033 h , p3rbce for more detail. r2bw_th2 11:8 rw port 2 receive bandwidth maximum[7:4]. see register 0033 h , p2rbce for more detail. r1bw_th2 7:4 rw port 1 receive bandwidth maximum[7:4]. see register 0033 h , p1rbce for more detail. r0bw_th2 3:0 rw port 0 receive bandwidth maximum[7:4]. see register 0033 h , p0rbce for more detail. ebc2 offset reset value extended bandwidth control register 2 36 h 0000 h field bits type description t1bw_th2 15:12 rw port 1 transmit bandwidth maximum[7:4] see register 0033 h , p1tbce for more detail. t0bw_th2 11:8 rw port 0 transmit bandwidth maximum[7:4]. see register 0033 h , p0tbce for more detail. r5bw_th2 7:4 rw port 5 receive bandwidth maximum[7:4]. see register 0033 h , p5rbce for more detail. r4bw_th2 3:0 rw port 4 receive bandwidth maximum[7:4]. see register 0033 h , p4rbce for more detail. uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 7%:b7+ uz 7%:b7+ uz 5%:b7+ uz 5%:b7+
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 116 rev. 1.31, 2005-12-05 extended bandwidth control register 4 ebc3 offset reset value extended bandwidth control register 3 37 h 0000 h field bits type description t5bw_th2 15:12 rw port 5 transmit bandwidth maximum[7:4]. see register 0033 h , p5tbce for more detail. t4bw_th2 11:8 rw port 4 transmit bandwidth maximum[7:4]. see register 0033 h , p4tbce for more detail. t3bw_th2 7:4 rw port 3 transmit bandwidth maximum[7:4]. see register 0033 h , p3tbce for more detail. t2bw_th2 3:0 rw port 2 transmit bandwidth maximum[7:4]. see register 0033 h , p2tbce for more detail. ebc4 offset reset value extended bandwidth control register 4 38 h 0000 h field bits type description fmdix0 15 rw port 0 mdix control this bit can be used for port 0 mdi/mdix selection. it is useful when port 0 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b using mdi 1 b using mdix r4bw_th3 14:12 rw port 4 receive bandwidth maximum[10:8]. see register 0033 h , p4rbce for more detail. r3bw_th3 11:9 rw port 3 receive bandwidth maximum[10:8]. see register 0033 h , p3rbce for more detail. r2bw_th3 8:6 rw port 2 receive bandwidth maximum[10:8]. see register 0033 h , p2rbce for more detail. r1bw_th3 5:3 rw port 1 receive bandwidth maximum[10:8]. see register 0033 h , p1rbce for more detail. uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz )0', ; uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+
data sheet 117 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description extended bandwidth control register 5 default vlan member and extended bandwidth control register 6 r0bw_th3 2:0 rw port 0 receive bandwidth maximum[10:8]. see register 0033 h , p0rbce for more detail. ebc5 offset reset value extended bandwidth control register 5 39 h 0000 h field bits type description fmdix1 15 r port 1 mdix control this bit can be used for port 1 mdi/mdix selection. it is useful when port 1 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b using mdi 1 b using mdix t3bw_th3 14:12 rw port 3 transmit bandwidth maximum[10:8]. see register 0033 h , p3tbce for more detail. t2bw_th3 11:9 rw port 2 transmit bandwidth maximum[10:8]. see register 0033 h , p2tbce for more detail. t1bw_th3 8:6 rw port 1 transmit bandwidth maximum[10:8]. see register 0033 h , p1tbce for more detail. t0bw_th3 5:3 rw port 0 transmit bandwidth maximum[10:8]. see register 0033 h , p0tbce for more detail. r5bw_th3 2:0 rw port 5 receive bandwidth maximum[10:8]. see register 0033 h , p5rbce for more detail. dvmebc6 offset reset value default vlan member and extended bandwidth control register 6 3a h 0fc0 h field bits type description u )0', ; uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 5%:b7+ uz 5hv uz '90 uz 7%:b7+ uz 7%:b7+
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 118 rev. 1.31, 2005-12-05 new storm register 0 new storm register 1 field bits type description res 15:12 rw reserved dvm 11:6 rw default vlan member always 111111 b t5bw_th3 5:3 rw port 5 transmit bandwidth maximum[10:8]. see register 0033 h , p5tbce for more detail. t4bw_th3 2:0 rw port 4 transmit bandwidth maximum[10:8]. see register 0033 h , p4tbce for more detail. ns0 offset reset value new storm register 0 3b h 0000 h field bits type description res 15 r reserved storm_dro p_en 14 rw storm drop enable 0 b do not drop in the storming period 1 b drop in the storming period storm_en 13 rw storm enable 0 b disable adm6996lc/lcx/lhx style broadcast storm protection 1 b enable adm6996lc/lcx/lhx style broadcast storm protection storm_100_ th 12:0 rw 100m threshold see table 31 for more detail information. it is used when all ports link up in the 100m. the upper bound is reached when the number of the packets received during the 50 ms is over 100m threshold. ns1 offset reset value new storm register 1 3c h 0000 h u 5hv uz 6725 0b' uz 6725 0b(1 uz 67250bb7+ uz )0', ; uz )0', ; uz )0', ; uz 67250bb7+
data sheet 119 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description new reserve address control register 0 field bits type description fmdix4 15 rw port 4 mdix control this bit can be used for port 4 mdi/mdix selection. it is useful when port 4 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b using mdi 1 b using mdix fmdix3 14 rw port 3 mdix control this bit can be used for port 3 mdi/mdix selection. it is useful when port 3 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b using mdi 1 b using mdix fmdix2 13 rw port 2 mdix control this bit can be used for port 2 mdi/mdix selection. it is useful when port 2 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b using mdi 1 b using mdix storm_10_t h 12:0 rw 10m threshold see table 31 for more detail information. it is used when one of ports link up in the 10m. the upper bound is reached when the number of the packets received during the 50 ms is over 10m threshold. nrac0 offset reset value new reserve address control register 0 3d h 00fd h field bits type description nrtb 15:14 rw new reserve txtag for bpdu 00 b system default tag 01 b unmodified 10 b always tagged 11 b always untagged pg 13:12 rw pri for gxrp 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 uz 157% uz 3* uz 35,b6 uz 35,b% uz 533 uz 533 uz *33 uz 533 uz 533 uz 333 uz 633 uz %33
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 120 rev. 1.31, 2005-12-05 new reserve address control register 1 pri_s 11:10 rw pri for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 pri_b 9:8 rw pri for bpdu 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 r3pp 7 rw reser_r3 pass portmap 0 b reser_r3 pass portmap is 000000 b 1 b reser_r3 pass pormap is 111111 b r2pp 6 rw reser_r2 pass portmap 0 b reser_r2 pass portmap is 000000 b 1 b reser_r2 pass pormap is 111111 b gpp 5 rw gxrp pass portmap 0 b gxrp pass portmap is 000000 b 1 b gxrp pass pormpap is 111111 b r1pp 4 rw reser_r1 pass portmap 0 b reser_r1 pass portmap is 000000 b 1 b reser_r1 pass portmap is 111111 b r0pp 3 rw reser_r0 pass portmap 0 b reser_r0 pass portmap is 000000 b 1 b reser_r0 pass portmap is 111111 b ppp 2 rw pae pass portmap 0 b pae pass portmap is 000000 b 1 b pae pass portpap is 111111 b spp 1 rw slow pass portmap 0 b slow pass portmap is 000000 b 1 b slow pass portpap is 111111 b bpp 0 rw bpdu pass portmap 0 b bpdu pass portmap is 000000 b 1 b bpdu pass portpap is 111111 b nrac1 offset reset value new reserve address control register 1 3e h 0000 h field bits type description uz 5hv uz 150* uz 1506 uz 050% uz 156* uz 1566 uz 156% uz 15&* uz 15&6 uz 15&% uz 157* uz 1576
data sheet 121 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description 5.2 eeprom extended registers field bits type description res 15:13 rw reserved nrmg 12 rw new reserve management for gxrp 0 b do not identify as management packets 1 b identify as management packets nrms 11 rw new reserve management for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b do not identify as management packets 1 b identify as management packets mrmb 10 rw new reserve management for bpdu 0 b do not identify as management packets 1 b identify as management packets nrsg 9 rw new reserve span.for gxrp 0 b do not identify as management packets 1 b identify as management packets nrss 8 rw new reserve span for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b do not identify as span packets 1 b identify as span packets nrsb 7 rw new reserve span for bpdu 0 b do not identify as span packets 1 b identify as span packets nrcg 6 rw new reserve cross_vlan for gxrp 0 b follow vlan 1 b cross vlan nrcs 5 rw new reserve cross_vlan. for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b follow vlan 1 b cross vlan nrcb 4 rw new reserve cross_vlan for bpdu 0 b follow vlan 1 b cross vlan nrtg 3:2 rw new reserve txtag for gxrp 00 b system default tag 01 b unmodified 10 b always tagged 11 b always untagged nrts 1:0 rw new reserve txtag for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 00 b system default tag 01 b unmodified 10 b always tagged 11 b always untagged
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 122 rev. 1.31, 2005-12-05 vlan filter 0 low similar registers vf0l offset reset value vlan filter 0 low 40 h 003f h field bits type description fid 15:12 rw fid the forwarding or learning group that the vid is assigned. tm 11:6 rw tagged member these bits indicate which ports associated with the vid should transmit tagged packets.tagged member[x] description. 0 b port x should transmit untagged packets 1 b port x should transmit tagged packets m5:0rw member these bits indicate which ports are the members of the vlan.member[x] description. 0 b port x is not a vlan member 1 b port x is a vlan member table 40 vfxl registers register short name register long name offset address page number vf1l vlan filter 1 low 42 h vf2l vlan filter 2 low 44 h vf3l vlan filter 3low 46 h vf4l vlan filter 4 low 48 h vf5l vlan filter 5 low 4a h vf6l vlan filter 6 low 4c h vf7l vlan filter 7 low 4e h vf8l vlan filter 8 low 50 h vf9l vlan filter 9 low 52 h vf10l vlan filter 10 low 54 h vf11l vlan filter 11 low 56 h vf12l vlan filter 12 low 58 h vf13l vlan filter 13 low 5a h vf14l vlan filter 14 low 5c h vf15l vlan filter 15 low 5e h uz ),' uz 70 uz 0
data sheet 123 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description vlan filter 0 high similar registers all vfxh registers have the same structure and characteristics, see vf0h . the offset addresses of the other vfxh registers are listed in table 41 . vf0h offset reset value vlan filter 0 high 41 h 8001 h field bits type description vv 15 rw vlan_valid 0 b vlan filter is not valid 1 b vlan filter is valid vp 14:12 rw vlan pri it indicates the vlan priority associated with vid. vid 11:0 rw vid it indicates the vlan id that is associated with fid, tagged member, member and vlan pri. table 41 vfxh registers register short name register long name offset address page number vf1h vlan filter 1 high 43 h vf2h vlan filter 2 high 45 h vf3h vlan filter 3 high 47 h vf4h vlan filter 4 high 49 h vf5h vlan filter 5 high 4b h vf6h vlan filter 6 high 4d h vf7h vlan filter 7 high 4f h vf8h vlan filter 8 high 51 h vf9h vlan filter 9 high 53 h vf10h vlan filter 10 high 55 h vf11h vlan filter 11 high 57 h vf12h vlan filter 12 high 59 h vf13h vlan filter 13 high 5b h vf14h vlan filter 14 high 5d h vf15h vlan filter 15 high 5f h uz 99 uz 93 uz 9,'
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 124 rev. 1.31, 2005-12-05 type filter 0 similar registers all tfx registers have the same structure and characteristics, see tf0 . the offset addresses of the other tfx registers are listed in table 42 . protocol filter 1 and 0 tf0 offset reset value type filter 0 60 h 0000 h field bits type description vcet 15:0 rw value compared with ether-type table 42 tfx registers register short name register long name offset address page number tf1 type filter 1 61 h tf2 type filter 2 62 h tf3 type filter 3 63 h tf4 type filter 4 64 h tf5 type filter 5 65 h tf6 type filter 6 66 h tf7 type filter 7 67 h pf_1_0 offset reset value protocol filter 1 and 0 68 h 0000 h field bits type description pfr1 15:8 rw value compared with protocol in ip header (protocol filter 1, 3, 5, 7) uz 9&(7 uz 3)5 uz 3)5
data sheet 125 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description similar registers all pfx registers have the same structure and characteristics, see pf_1_0 . the offset addresses of the other pfx registers are listed in table 43 . tcp/udp filter 0 similar registers all tufx registers have the same structure and characteristics, see tuf0 . the offset addresses of the other tufx registers are listed in table 46 . pfr0 7:0 rw value compared with protocol in ip header (protocol filter 0, 2, 4, 6) table 43 pfx registers register short name register long name offset address page number pf_3_2 protocol filter 3 and 2 68 h pf_5_4 protocol filter 5 and 4 69 h pf_7_6 protocol filter 7 and 6 6a h tuf0 offset reset value tcp/udp filter 0 8c h 0000 h field bits type description val_comp 15:0 rw value compared with the destinat ion port number in the tcp/udp header table 44 tufx registers register short name register long name offset address page number tuf1 tcp/udp filter 1 8d h tuf2 tcp/udp filter 2 8e h tuf3 tcp/udp filter 3 8f h tuf4 tcp/udp filter 4 90 h tuf5 tcp/udp filter 5 91 h tuf6 tcp/udp filter 6 92 h tuf7 tcp/udp filter 7 93 h field bits type description uz 9$/b&203
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 126 rev. 1.31, 2005-12-05 type filter action protocol filter action tfa offset reset value type filter action 94 h 0000 h field bits type description atf7 15:14 rw action for type filter 7 see register 0094 h , atf0 for more detail. atf6 13:12 rw action for type filter 6 see register 0094 h , atf0 for more detail. atf5 11:10 rw action for type filter 5 see register 0094 h , atf0 for more detail. atf4 9:8 rw action for type filter 4 see register 0094 h , atf0 for more detail. atf3 7:6 rw action for type filter 3 see register 0094 h , atf0 for more detail. atf2 5:4 rw action for type filter 2 see register 0094 h , atf0 for more detail. atf1 3:2 rw action for type filter 1 see register 0094 h , atf0 for more detail. atf0 1:0 rw action for type filter 0 00 b type portmap is default output ports 01 b type portmap is 000000 b 10 b type portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains defa ult output ports , excluding the cpu port 11 b type portmap contains defa ult output ports , excluding the cpu port pfa offset reset value protocol filter action 95 h 0000 h uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3)
data sheet 127 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description tcp/udp action 0 field bits type description apf7 15:14 rw action for protocol filter 7 see register 0095 h , apf0 for more detail. apf6 13:12 rw action for protocol filter 6 see register 0095 h , apf0 for more detail. apf5 11:10 rw action for protocol filter 5 see register 0095 h , apf0 for more detail. apf4 9:8 rw action for protocol filter 4 see register 0095 h , apf0 for more detail. apf3 7:6 rw action for protocol filter 3 see register 0095 h , apf0 for more detail. apf2 5:4 rw action for protocol filter 2 see register 0095 h , apf0 for more detail. apf1 3:2 rw action for protocol filter 1 see register 0095 h , apf0 for more detail. apf0 1:0 rw action for protocol filter 0 00 b protocol portmap is default output ports 01 b protocol portmap is 000000 b 10 b protocol portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains defa ult output ports , excluding the cpu port 11 b protocol portmap contains defa ult output ports , excluding the cpu port tua0 offset reset value tcp/udp action 0 96 h 0000 h field bits type description atuf3 15:14 rw action for tcp/udp filter 3. see register 0096 h , atuf0 for more detail. tupf3 13:12 rw tcp/udp pri for tcp/udp filter 3 see register 0096 h , tupf0 for more detail. atuf2 11:10 rw action for tcp/udp filter 2 see register 0096 h , atuf0 for more detail. tupf2 9:8 rw tcp/udp pri for tcp/udp filter 2 see register 0096 h , tupf0 for more detail. uz $78) uz 783) uz $78) uz 783) uz $78) uz 783) uz $78) uz 783)
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 128 rev. 1.31, 2005-12-05 tcp/udp action 1 atuf1 7:6 rw action for tcp/udp filter 1 see register 0096 h , atuf0 for more detail. tupf1 5:4 rw tcp/udp pri for tcp/udp filter 1 see register 0096 h , tupf0 for more detail. atuf0 3:2 rw action for tcp/udp filter 0 00 b protocol portmap is default output ports 01 b protocol portmap is 000000 b 10 b protocol portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains defa ult output ports , excluding the cpu port 11 b protocol portmap contains defa ult output ports , excluding the cpu port tupf0 1:0 rw tcp/udp pri for tcp/udp filter 0 00 b queue 0 01 b queue 1 10 b queue 2 11 b queue 3 tua1 offset reset value tcp/udp action 1 97 h 0000 h field bits type description atuf7 15:14 rw action for tcp/udp filter 7 see register 0096 h , atuf0 for more detail. tupf7 13:12 rw tcp/udp pri for tcp/udp filter 7 see register 0096 h , tupf0 for more detail. atuf6 11:10 rw action for tcp/udp filter 6 see register 0096 h , atuf0 for more detail. tupf6 9:8 rw tcp/udp pri for tcp/udp filter 6 see register 0096 h , tupf0 for more detail. atuf5 7:6 rw action for tcp/udp filter 5 see register 0096 h , atuf0 for more detail. tupf5 5:4 rw tcp/udp pri for tcp/udp filter 5 see register 0096 h , tupf0 for more detail. atuf4 3:2 rw action for tcp/udp filter 4 see register 0096 h , atuf0 for more detail. field bits type description uz $78) uz 783) uz $78) uz 783) uz $78) uz 783) uz $78) uz 783)
data sheet 129 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description tcp/udp action 2 tupf4 1:0 rw tcp/udp pri for tcp/udp filter 4 see register 0096 h , tupf0 for more detail. tua2 offset reset value tcp/udp action 2 98 h 0000 h field bits type description res 15:14 r reserved comp 13:12 rw compare tcp/udp source port or destination port 00 b do not compare 01 b compare destination port 10 b compare source port 11 b compare destination port or source port p5i 11 rw port 5 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p4i 10 rw port 4 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p3i 9 rw port 3 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p2i 8 rw port 2 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p1i 7 rw port 1 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p0i 6 rw port 0 ip over tcp/udp 0 b use tcp/udp field when packets contain both tcp/udp and ip 1 b use ip field when packets contain both tcp/udp and ip p5t 5 rw port 5 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority p4t 4 rw port 4 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority field bits type description u 5hv uz &203 uz 3, uz 3, uz 3, uz 3, uz 3, uz 3, uz 37 uz 37 uz 37 uz 37 uz 37 uz 37
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 130 rev. 1.31, 2005-12-05 interrupt enable register interrupt status register p3t 3 rw port 3 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority p2t 2 rw port 2 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority p1t 1 rw port 1 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority p0t 0 rw port 0 tcp/udp prien 0 b do not use tcp/udp priority 1 b use tcp/udp priority ie offset reset value interrupt enable register 9a h 0000 h field bits type description res 15:9 r reserved ltadie 8 rw leaning table access done interrupt enable 0 b interrupt disable 1 b interrupt enable psie 7:2 rw port security interrupt enable it?s a per port setting 0 b interrupt disable 1 b interrupt enable coie 1 rw counter overflow interrupt enable 0 b interrupt disable 1 b interrupt enable psie 0 rw port status in terrupt enable 0 b interrupt disable 1 b interrupt enable is offset reset value interrupt status register 9b h 0000 h field bits type description u 5hv uz /7$' ,( uz 36,( uz &2,( uz 36,(
data sheet 131 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description 5.3 counter and switch status registers chip identifier 0 chip identifier 1 field bits type description res 15:9 r reserved ltad 8 lhsc leaning table access done 0 b access does not end 1 b access end psv 7:2 lhsc port security violation it?s a per port setting 0 b security did not violate 1 b security violated co 1 lhsc counter overflow 0 b overflow did not happen 1 b overflow happened for any of the counters psc 0 lhsc port status change 0 b no status (link, speed, duplex, flow control) changed for any port 1 b status changed for any of 6 ports ci0 offset reset value chip identifier 0 a0 h 1022 h field bits type description pc 15:4 ro product code[11:0] vn 3:0 ro version number ci1 offset reset value chip identifier 1 a1 h 0007 h u 5hv okvf /7$' okvf 369 okvf &2 okvf 36& ur 3& ur 91
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 132 rev. 1.31, 2005-12-05 port status 0 field bits type description res 15:4 ro reserved pc 3:0 ro product code[ 15:12 ] ps0 offset reset value port status 0 a2 h 0000 h field bits type description res 15:12 ro reserved p1fcs 11 ro port 1 flow control status 0 b port 1 disables the full flow control/half back pressure function 1 b port 1 enabled the full flow control/half back pressure function p1ds 10 ro port 1 duplex status 0 b port 1 operates in the half duplex 1 b port 1 operates in the full duplex p1ss 9 ro port 1 speed status 0 b port 1 operates in the 10m 1 b port 1 operates in the 100m p1ls 8 ro port 1 link status 0 b port 1 links down 1 b port 1 links up res 7:4 ro reserved p0fcs 3 ro port 0 flow control status 0 b port 0 disables the full flow control/half back pressure function 1 b port 0 enabled the full flow control/half back pressure function p0ds 2 ro port 0 duplex status 0 b port 0 operates in the half duplex 1 b port 0 operates in the full duplex p0ss 1 ro port 0 speed status 0 b port 0 operates in the 10m 1 b port 0 operates in the 100m ur 5hv ur 3& ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6
data sheet 133 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description port status 1 p0ls 0 ro port 0 link status 0 b port 0 links down 1 b port 0 links up ps1 offset reset value port status 1 a3 h 0000 h field bits type description p4fcs 15 ro port 4 flow control status 0 b port 4 disables the full flow control/half back pressure function 1 b port 4 enabled the full flow control/half back pressure function p4ds 14 ro port 4 duplex status 0 b port 4 operates in the half duplex 1 b port 4 operates in the full duplex p4ss 13 ro port 4 speed status 0 b port 4 operates in the 10m 1 b port 4 operates in the 100m p4ls 12 ro port 4 link status 0 b port 4 links down 1 b port 4 links up p3fcs 11 ro port 3 flow control status 0 b port 3 disables the full flow control/half back pressure function 1 b port 3 enabled the full flow control/half back pressure function p3ds 10 ro port 3 duplex status 0 b port 3 operates in the half duplex 1 b port 3 operates in the full duplex p3ss 9 ro port 3 speed status 0 b port 3 operates in the 10m 1 b port 3 operates in the 100m p3ls 8 ro port 3 link status 0 b port 3 links down 1 b port 3 links up. res 7:4 ro reserved p2fcs 3 ro port 2 flow control status 0 b port 2 disables the full flow control/half back pressure function 1 b port 2 enabled the full flow control/half back pressure function field bits type description ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 134 rev. 1.31, 2005-12-05 port status 2 counter low 0 p2ds 2 ro port 2 duplex status 0 b port 2 operates in the half duplex 1 b port 2 operates in the full duplex p2ss 1 ro port 2 speed status 0 b port 2 operates in the 10m 1 b port 2 operates in the 100m p2ls 0 ro port 2 link status 0 b port 2 links down 1 b port 2 links up ps2 offset reset value port status 2 a4 h 0000 h field bits type description res 15:5 ro reserved p5fce 4 ro port 5 flow control enable 0 b port 5 disables the full flow control/half back pressure function 1 b port 5 enabled the full flow control/half back pressure function p5ds 3 ro port 5 duplex status 0 b port 5 operates in the half duplex 1 b port 5 operates in the full duplex res 2 ro reserved p5ss 1 ro port 5 speed status 0 b port 5 operates in the 10m 1 b port 5 operates in the 100m p5ls 0 ro port 5 link status 0 b port 5 links down 1 b port 5 links up cl0 offset reset value port 0 receive packet counter low a8 h 0000 h field bits type description ur 5hv ur 3)& ( ur 3'6 ur 5hv ur 366 ur 3/6
data sheet 135 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description similar registers all clx registers have the same structure and characteristics, see cl0 . the offset addresses of the other clx registers are listed in table 45 . field bits type description counter 15:0 rw counter[15:0] table 45 clx registers register short name register long name offset address page number cl1 port 1 receive packet counter low ac h cl2 port 2 receive packet counter low b0 h cl3 port 3 receive packet counter low b4 h cl4 port 4 receive packet counter low b6 h cl5 port 5 receive packet counter low b8 h cl6 port 0 receive packet byte count low ba h cl7 port 1 receive packet byte count low be h cl8 port 2 receive packet byte count low c2 h cl9 port 3 receive packet byte count low c6 h cl10 port 4 receive packet byte count low c8 h cl11 port 5 receive packet byte count low ca h cl12 port 0 transmit packet count low cc h cl13 port 1 transmit packet count low d0 h cl14 port 2 transmit packet count low d4 h cl15 port 3 transmit packet count low d8 h cl16 port 4 transmit packet count low da h cl17 port 5 transmit packet count low dc h cl18 port 0 transmit packet byte count low de h cl19 port 1 transmit packet byte count low e2 h cl20 port 2 transmit packet byte count low e6 h cl21 port 3 transmit packet byte count low ea h cl22 port 4 transmit packet byte count low ec h cl23 port 5 transmit packet byte count low ee h cl24 port 0 collision count low f0 h cl25 port 1 collision count low f4 h cl26 port 2 collision count low f8 h cl27 port 3 collision count low fc h cl28 port 4 collision count low fe h cl29 port 5 collision count low 100 h uz &2817(5
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 136 rev. 1.31, 2005-12-05 counter high 0 similar registers all chx registers have the same structure and characteristics, see ch0 . the offset addresses of the other clh registers are listed in table 46 . cl30 port 0 error count low 102 h cl31 port 1 error count low 106 h cl32 port 2 error count low 10a h cl33 port 3 error count low 10e h cl34 port 4 error count low 110 h cl35 port 5 error count low 112 h ch0 offset reset value port 0 receive packet counter high a9 h 0000 h field bits type description counter 15:0 rw counter[31:16] table 46 chx registers register short name register long name offset address page number ch1 port 1 receive packet counter high ad h ch2 port 2 receive packet counter high b1 h ch3 port 3 receive packet counter high b5 h ch4 port 4 receive packet counter high b7 h ch5 port 5 receive packet counter high b9 h ch6 port 0 receive packet byte count high bb h ch7 port 1 receive packet byte count high bf h ch8 port 2 receive packet byte count high c3 h ch9 port 3 receive packet byte count high c7 h ch10 port 4 receive packet byte count high c9 h ch11 port 5 receive packet byte count high cb h ch12 port 0 transmit packet count high cd h ch13 port 1 transmit packet count high d1 h ch14 port 2 transmit packet count high d5 h table 45 clx registers (cont?d) register short name register long name offset address page number uz &2817(5
data sheet 137 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description over-flow flag 0 ch15 port 3 transmit packet count high d9 h ch16 port 4 transmit packet count high db h ch17 port 5 transmit packet count high dd h ch18 port 0 transmit packet byte count high df h ch19 port 1 transmit packet byte count high e3 h ch20 port 2 transmit packet byte count high e7 h ch21 port 3 transmit packet byte count high eb h ch22 port 4 transmit packet byte count high ed h ch23 port 5 transmit packet byte count high ef h ch24 port 0 collision count high f1 h ch25 port 1 collision count high f5 h ch26 port 2 collision count high f9 h ch27 port 3 collision count high fd h ch28 port 4 collision count high ff h ch29 port 5 collision count high 101 h ch30 port 0 error count high 103 h ch31 port 1 error count high 107 h ch32 port 2 error count high 10b h ch33 port 3 error count high 10f h ch34 port 4 error count high 111 h ch35 port 5 error count high 113 h off0 offset reset value over-flow flag 0 114 h 0000 h field bits type description p3_bc 15 lhsc overflow of port 3 receive packet byte count 0 b no overflow 1 b overflow res 14 ro reserved p2_bc 13 lhsc overflow of port 2 receive packet byte count 0 b no overflow 1 b overflow table 46 chx registers (cont?d) register short name register long name offset address page number okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & okvf 3b& okvf 3b& okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b&
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 138 rev. 1.31, 2005-12-05 over-flow flag 1 res 12 ro reserved p1_bc 11 lhsc overflow of port 1 receive packet byte count 0 b no overflow 1 b overflow res 10 ro reserved p0_bc 9 lhsc overflow of port 0 receive packet byte count 0 b no overflow 1 b overflow p5_c 8 lhsc overflow of port 5 receive packet count 0 b no overflow 1 b overflow p4_c 7 lhsc overflow of port 4 receive packet count 0 b no overflow 1 b overflow p3_c 6 lhsc overflow of port 3 receive packet count 0 b no overflow 1 b overflow res 5 ro reserved p2_c 4 lhsc overflow of port 2 receive packet count 0 b no overflow 1 b overflow res 3 ro reserved p1_c 2 lhsc overflow of port 1 receive packet count 0 b no overflow 1 b overflow res 1 ro reserved p0_c 0 lhsc overflow of port 0 receive packet count 0 b no overflow 1 b overflow off1 offset reset value over-flow flag 1 115 h 0000 h field bits type description res 15:2 ro reserved field bits type description ur 5hv okvf 3b% & okvf 3b% &
data sheet 139 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description over-flow flag 2 p5_bc 1 lhsc overflow of port 5 receive packet byte count 0 b no overflow 1 b overflow p4_bc 0 lhsc overflow of port 4 receive packet byte count 0 b no overflow 1 b overflow off2 offset reset value over-flow flag 2 116 h 0000 h field bits type description p3_bc 15 lhsc overflow of port 3 transmit packet byte count 0 b no overflow 1 b overflow res 14 ro reserved p2_bc 13 lhsc overflow of port 2 transmit packet byte count 0 b no overflow 1 b overflow res 12 ro reserved p1_bc 11 lhsc overflow of port 1 transmit packet byte count 0 b no overflow 1 b overflow res 10 ro reserved p0_bc 9 lhsc overflow of port 0 transmit packet byte count 0 b no overflow 1 b overflow p5_c 8 lhsc overflow of port 5 transmit packet count 0 b no overflow 1 b overflow p4_c 7 lhsc overflow of port 4 transmit packet count 0 b no overflow 1 b overflow p3_c 6 lhsc overflow of port 3 transmit packet count 0 b no overflow 1 b overflow res 5 ro reserved field bits type description okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & okvf 3b& okvf 3b& okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b&
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 140 rev. 1.31, 2005-12-05 over-flow flag 3 over-flow flag 4 p2_c 4 lhsc overflow of port 2 transmit packet count 0 b no overflow 1 b overflow res 3 ro reserved p1_c 2 lhsc overflow of port 1 transmit packet count 0 b no overflow 1 b overflow res 1 ro reserved p0_c 0 lhsc overflow of port 0 transmit packet count 0 b no overflow 1 b overflow off3 offset reset value over-flow flag 3 117 h 0000 h field bits type description res 15:2 ro reserved p5_bc 1 lhsc overflow of port 5 transmit packet byte count 0 b no overflow 1 b overflow p4_bc 0 lhsc overflow of port 4 transmit packet byte count 0 b no overflow 1 b overflow off4 offset reset value over-flow flag 4 118 h 0000 h field bits type description ur 5hv okvf 3b% & okvf 3b% & okvf 3(& ur 5hv okvf 3(& ur 5hv okvf 3(& ur 5hv okvf 3(& okvf 3&& okvf 3&& okvf 3&& ur 5hv okvf 3&& ur 5hv okvf 3&& ur 5hv okvf 3&&
data sheet 141 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description over-flow flag 5 field bits type description p3ec 15 lhsc overflow of port 3 error count 0 b no overflow 1 b overflow res 14 ro reserved p2ec 13 lhsc overflow of port 2 error count 0 b no overflow 1 b overflow res 12 ro reserved p1ec 11 lhsc overflow of port 1 error count 0 b no overflow 1 b overflow res 10 ro reserved p0ec 9 lhsc overflow of port 0 error count 0 b no overflow 1 b overflow p5cc 8 lhsc overflow of port 5 collision count 0 b no overflow 1 b overflow p4cc 7 lhsc overflow of port 4 collision count 0 b no overflow 1 b overflow p3cc 6 lhsc overflow of port 3 collision count 0 b no overflow 1 b overflow res 5 ro reserved p2cc 4 lhsc overflow of port 2 collision count 0 b no overflow 1 b overflow res 3 ro reserved p1cc 2 lhsc overflow of port 1 collision count 0 b no overflow 1 b overflow res 1 ro reserved p0cc 0 lhsc overflow of port 0 collision count 0 b no overflow 1 b overflow off5 offset reset value over-flow flag 5 119 h 0000 h
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 142 rev. 1.31, 2005-12-05 hardware setting low register hardware setting high register field bits type description res 15:2 ro reserved p5ec 1 lhsc overflow of port 5 error count 0 b no overflow 1 b overflow p4ec 0 lhsc overflow of port 4 error count 0 b no overflow 1 b overflow hsl offset reset value hardware setting low register 130 h 0000 h field bits type description h15ro resreved bo 14 ro bond daf 13 ro disable adm6996lc/lcx/lhx function bp 12 ro bpen db 11 ro 16/32 bit data bus gm 10 ro gpsi mode rm 9 ro rmii mode p4it 8:7 ro port 4 interface type gfc 6 ro global flow control p4fm 5 ro port 4 fiber mode dc 4 ro dual color ca 3:2 ro chip address ac 1 ro auto-crossover an 0 ro auto-negotiation ur 5hv okvf 3(& okvf 3(& ur + ur %2 ur '$) ur %3 ur '% ur *0 ur 50 ur 3,7 ur *)& ur 3)0 ur '& ur &$ ur $& ur $1
data sheet 143 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description assign option register hsh offset reset value hardware setting high register 131 h 0000 h field bits type description res 15:10 ro reserved ltbr 9 ro learning table bist result 0 b work 1 b do not work lltbr 8 ro linklist table bist result (linklist table does not do bist test in normal mode) 0 b work 1 b do not work ctbr 7 ro control table bist result 0 b work 1 b do not work hitbr 6 ro hardware igmp table bist result 0 b work 1 b do not work dbbr 5 ro data buffer bist result 0 b work 1 b do not work p5m 4:3 ro p5 mode 00 b gpsi 01 b rmii 10 b mii p4m 2:1 ro p4 mode 00 b port 4 uses inner phy 01 b port 4 uses mii 11 b port 4 isolated phy cfg 0 ro cfg ao offset reset value assign option register 135 h 0000 h ur 5hv ur /7%5 ur //7% 5 ur &7%5 ur +,7% 5 ur '%%5 ur 30 ur 30 ur &)*
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 144 rev. 1.31, 2005-12-05 security violation port security status 0 field bits type description res 15:7 r reserved af 6:3 rw assign fid it is used for assign lock fid. ap 2:0 rw assign port it is used for the port that the user wants to assign or for the monitor port. svp offset reset value security violation port 138 h 0000 h field bits type description res 15:12 r reserved psi 11:6 rc port source intrusion 0 b source intrusion did not happen 1 b source intrusion happened res 5:0 r reserved ss0 offset reset value security status 0 139 h 0000 h u 5hv uz $) uz $3 u 5hv uf 36, u 5hv u 5hv u )/ u 3/
data sheet 145 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description security status 1 first lock address search field bits type description res 15:12 r reserved fl 11:6 r first lock 0 b port did not lock the address 1 b port locked the address pl 5:0 r port locked 0 b port did not close 1 b port closed because of source violation ss1 offset reset value security status 1 13a h 0000 h field bits type description res 15:6 r reserved ll 5:0 r link lock 0 b link lock did not happen 1 b link lock happened flas offset reset value first lock address search 13b h 0000 h field bits type description res 15:3 r reserved u 5hv u // u 5hv uz )/63
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 146 rev. 1.31, 2005-12-05 first lock address [15:0] first lock address [31:16] first lock address [47:32] flsp 2:0 rw first lock search port users could write this register to get the lock address and the lock fid (returned in the 13c h , 13d h , 13e h , 13f h ) associated with the port. 000 b search the address and fid locked on the port 0 001 b search the address and fid locked on the port 1 010 b search the address and fid locked on the port 1 011 b search the address and fid locked on the port 1 100 b search the address and fid locked on the port 1 101 b search the address and fid locked on the port 1 fla1 offset reset value first lock address [15:0] 13c h 0000 h field bits type description fla 15:0 r first lock address [15:0] fla2 offset reset value first lock address [31:16] 13d h 0000 h field bits type description fla 15:0 r first lock address [31:16] fla3 offset reset value first lock address [47:32] 13e h 0000 h field bits type description u )/$ u )/$
data sheet 147 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description first lock fid counter control low register field bits type description fla 15:0 r first lock address [47:32] flf offset reset value first lock fid 13f h 0000 h field bits type description res 15:4 r reserved flf 3:0 r first lock fid ccl offset reset value counter control low register 140 h 0000 h field bits type description res 15:8 r reserved bas 7 rw busy/access start 0 b the counter control is free 1 b the counter control is busy, or users should write 1 b into this bit to start the access when the engine is free u )/$ u 5hv u )/) u 5hv uz %$6 uz & uz ,5&b53&
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 148 rev. 1.31, 2005-12-05 counter status low register counter status high register 5.4 phy registers phy control register of port 0 c6rw counter 0 b indirect read counter 1 b renew port counter irc_rpc 5:0 rw indirect read counter it means the counter address renew port counter it means the counters on each port to renew csl offset reset value counter status low register 142 h 0000 h field bits type description counter 15:0 r counter [15:0] csh offset reset value counter status high register 143 h 0000 h field bits type description counter 15:0 r counter [31:16] field bits type description u &2817(5 u &2817(5
data sheet 149 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description phy_c0 offset reset value phy control register of port 0 200 h 3100 h field bits type description rst 15 rwsc reset setting this bit initiates the software reset function that resets the selected port, except for the phase-locked loop circuit. it will re-latch in all hardware configuration pin values the software reset process takes 25 s to complete. this bit, which is self-clearing, returns a value of 1 until the reset process is complete. 0 b normal operation 1 b phy reset lpbk 14 rw loop back enable this bit controls the phy loopback operation that isolates the network transmitter outputs (txp and txn) and routes the mii transmit data to the mii receive data path. this function should only be used when auto negotiation is disabled (bit 12 = 0). the specific phy (10base-t or 100base-x) used for this operation is determined by bits 12 and 13 of this register 0 b disable loopback mode 1 b enable loopback mode speed_lsb 13 rw speed selection lsb, 0.6, 0.13 link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored).if it is fiber mode, 0.13 is always 1. any write to this bit will have no effect. 00 b 10 mbit/s 01 b 100 mbit/s 10 b 1000 mbit/s 11 b reserved anen 12 rw auto negotiation enable this bit determines whether the link speed should set up by the auto negotiation process or not. it is set at power up or reset if the recanen pin detects a logic 1 input level in twisted-pair mode.if it is set when fiber mode is configured, any write to this bit will be ignored . 0 b disable auto negotiation process 1 b enable auto negotiation process uzvf 567 uz /3%. uz 63(( 'b/ uz $1(1 uz 3'1 uz ,62 uzvf $1(1 b567 uz '3/; uz &2/7 67 ur 63(( 'b0 5hv
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 150 rev. 1.31, 2005-12-05 similar registers all phy_cx registers have the same structure and characteristics, see phy_c0 . the offset addresses of the other phy_cx registers are listed in table 47 . pdn 11 rw power down enable ored result with pi_pwrdn pin. setting this bit high or asserting the pi_pwrdn puts the phy into power down mode. during the power down mode, txp/txn and all led outputs are tristated and the mii interfaces are isolated. 0 b normal operation 1 b power down iso 10 rw isolate phy from network setting this control bit isolates the part from the mii, with the exception of the serial management interface. when this bit is asserted, the phy does not respond to txd, txen and txer inputs, and it presents a high impedence on its txc, rxc, crsdv, rxer, rxd , col and crs outputs. 0 b normal operation 1 b isolate phy from mii anen_rst 9 rwsc restart auto negotiation setting this bit while auto negotiation is enabled forces a new auto negotiation process to start. this bit is self-clearing and returns to 0 after the auto negotiation process has commenced. 0 b normal operation 1 b restart auto negotiation process dplx 8 rw duplex mode if auto negotiation is disabled, this bit determines the duplex mode for the link. 0 b half duplex mode 1 b full duplex mode coltst 7 rw collision test when set, this bit will cause the col signal of mii interface to be asserted in response to the assertion of txen. 0 b disable col signal test 1 b enable col signal test speed_msb 6 ro speed selection msb set to 0 all the time indicate that the phy does not support 1000 mbit/s function. table 47 phy_cx registers register short name register long name offset address page number phy_c1 phy control register of port 1 220 h phy_c2 phy control register of port 2 240 h phy_c3 phy control register of port 3 260 h phy_c4 phy control register of port 4 280 h field bits type description
data sheet 151 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description phy status register of port 0 phy_s0 offset reset value phy status register of port 0 201 h 7849 h field bits type description cap_t4 15 ro 100base-t4 capable set to 0 all the time to indicate that the phy does not support 100base-t4 cap_txf 14 ro 100base-x full duplex capable set to 1 all the time to indicate that the phy does support full duplex mode cap_txh 13 ro 100base-x half duplex capable set to 1 all the time to indicate that the phy does support half duplex mode cap_tf 12 ro 10m full duplex capable tp : set to 1 all the time to indicate that the phy does support 10m full duplex mode fx : set to 0 all the time to indicate that the phy does not support 10m full duplex mode cap_th 11 ro 10m half duplex capable tp : set to 1 all the time to indicate that the phy does support 10m half duplex mode fx : set to 0 all the time to indicate that the phy does not support 10m half duplex mode cap_t2 10 ro 100base-t2 capable set to 0 all the time to indicate that the phy does not support 100base-t2 cap_supr 6 ro mf preamble suppression capable this bit is hardwired to 1 indicating that the phy accepts management frame without preamble. minimum 32 preamble bits are required following power-on or hardware reset. one idle bit is required between any two management transactions as per ieee 802.3u specification. an_comp 5 ro auto negotiation complete if auto negotiation is enabled, this bit indicates whether the auto negotiation process has been completed or not. set to 0 all the time when fiber mode is selected. 0 b auto negotiation process not completed 1 b auto negotiation process completed ur &$3b 7 ur &$3b 7;) ur &$3b 7;+ ur &$3b 7) ur &$3b 7+ ur &$3b 7 5hv ur &$3b 6835 ur $1b& 203 ur 5(0b )/7 ur &$3b $1(* ur /,1. ur -$% ur (;75 (*
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 152 rev. 1.31, 2005-12-05 similar registers all phy_sx registers have the same structure and characteristics, see phy_s0 . the offset addresses of the other phy_sx registers are listed in table 48 . phy identifier register of port 0 (a) rem_flt 4 ro remote fault detect this bit is latched to 1 if the rf bit in the auto negotiation link partner ability register (bit 13, register address 05 h ) is set or the receive channel meets the far end fault indication function criteria. it is unlatched when this register is read. 0 b remote fault not detected 1 b remote fault detected cap_aneg 3 ro auto negotiation ability tp : this bit is set to 1 all the time, indicating that phy is capable of auto negotiation. fx : this bit is set to 0 all the time, indicating that phy is not capable of auto negotiation in fiber mode. 0 b not capable of auto negotiation 1 b capable of auto negotiation link 2 ro link status this bit reflects the current state of the link ? test-fail state machine. loss of a valid link causes a 0 latched into this bit. it remains 0 until this register is read by the serial management interface. whenever linkup, this bit should be read twice to get link up status 0 b link is down 1 b link is up jab 1 ro jabber detect 0 b jabber condition not detected 1 b jabber condition detected extreg 0 ro extended capability this bit defaults to 1, indicating that the phy implements extended registers. 0 b no extended register set 1 b extended register set table 48 phy_sx registers register short name register long name offset address page number phy_s1 phy status register of port 1 221 h phy_s2 phy status register of port 2 241 h phy_s3 phy status register of port 3 261 h phy_s4 phy status register of port 4 281 h phy_i0_a offset reset value phy identifier register of port 0 (a) 202 h 0302 h field bits type description
data sheet 153 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description similar registers all phy_ix_a registers have the same structure and characteristics, see phy_i0_a . the offset addresses of the other phy_ix_a registers are listed in table 49 . phy identifier register of port 0 (b) similar registers all phy_ix_b registers have the same structure and characteristics, see phy_i0_b . the offset addresses of the other phy_ix_b registers are listed in table 50 . field bits type description phy_id 15:0 ro ieee address table 49 phy_ix_a registers register short name register long name offset address page number phy_i1_a phy identifier register of port 1 (a) 222 h phy_i2_a phy identifier register of port 2 (a) 242 h phy_i3_a phy identifier register of port 3 (a) 262 h phy_i4_a phy identifier register of port 4 (a) 282 h phy_i0_b offset reset value phy identifier register of port 0 (b) 203 h 6071 h field bits type description phy_id 15:10 ro ieee address model_id 9:4 ro ieee model no. rev_id 3:0 ro ieee revision no. table 50 phy_ix_b registers register short name register long name offset address page number phy_i1_b phy identifier register of port 1 (b) 223 h phy_i2_b phy identifier register of port 2 (b) 243 h ur 3+<b,' ur 3+<b,' ur 0rghob,' ur 5(9b,'
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 154 rev. 1.31, 2005-12-05 auto negotiation advertisement register of port 0 phy_i3_b phy identifier register of port 3 (b) 263 h phy_i4_b phy identifier register of port 4 (b) 283 h anap0 offset reset value auto negotiation advertisement register of port 0 204 h 05e1 h field bits type description np 15 ro next page this bit is defaults to 1, indicating that phy is next page capable rf 13 ro remote fault this bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. 0 b no remote fault has been detected 1 b remote fault has been detected asm_dir 11 rw asymmetric pause direction bit[ 11:10 ] capability 00 b no pause 01 b symmetric pause 10 b asymmetric pause toward link partner 11 b both symmetric pause and asymmetric pause toward local device pause 10 rw pause operation for full duplex value on paurec will be stored in this bit during power on reset. t4 9 ro technology ability for 100base-t4 defaults to 0. tx_fdx 8 rw 100base-tx full duplex 0 b not capable of 100m full duplex operation 1 b capable of 100m full duplex operation tx_hdx 7 rw 100base-tx half duplex 0 b not capable of 100m operation 1 b capable of 100m operation 10_fdx 6 rw 10base-t full duplex 0 b not capable of 10m full duplex operation 1 b capable of 10m full duplex operation table 50 phy_ix_b registers (cont?d) register short name register long name offset address page number ur 13 5hv ur 5) 5hv uz $60b ',5 uz 3$86 ( ur 7 uz 7;b) '; uz 7;b+ '; uz b) '; uz b+ '; ur 6)
data sheet 155 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description similar registers all anapx registers have the same structure and characteristics, see anap0 . the offset addresses of the other anapx registers are listed in table 51 . auto negotiation link partner ability register of port 0 10_hdx 5 rw 10base-t half duplex note: bit 8:5 should be combined with rec100, recful pin input to determine the finalized speed and duplex mode. 0 b not capable of 10m operation 1 b capable of 10m operation sf 4:0 ro selector field these 5 bits are hardwired to 00001 b , indicating that the phy supports ieee 802.3 csma/cd. table 51 anapx registers register short name register long name offset address page number anap1 auto negotiation advertisement register of port 1 224 h anap2 auto negotiation advertisement register of port 2 244 h anap3 auto negotiation advertisement register of port 3 264 h anap4 auto negotiation advertisement register of port 4 284 h anlpa0 offset reset value auto negotiation link partner ability register of port 0 205 h 01e1 h field bits type description npage 15 ro next page 0 b not capable of next page function 1 b capable of next page function ack 14 ro acknowledge 0 b not acknowledged 1 b link partner acknowledges reception of the ability data word rf 13 ro remote fault 0 b no remote fault has been detected 1 b remote fault has been detected lp_dir 11 ro link partner asymmetric pause direction field bits type description ur 13$* ( ur $&. ur 5) 5hv ur /3b' ,5 ur /3b3 $8 ur /3b7 ur /3b) '; ur /3b+ '; ur /3b) ur /3b+ ur 6)
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 156 rev. 1.31, 2005-12-05 similar registers all anlpax registers have the same structure and characteristics, see anlpa0 . the offset addresses of the other anlpax registers are listed in table 52 . auto negotiation expansion register of port 0 lp_pau 10 ro link partner pause capabilityvalue on paurec will be stored in this bit during power on reset. lp_t4 9 ro link partner technology ability for 100base-t4defaults to 0. lp_fdx 8 ro 100base-tx full duplex 0 b not capable of 100m full duplex operation 1 b capable of 100m full duplex operation lp_hdx 7 ro 100base-tx half duplex 0 b not capable of 100m operation 1 b capable of 100m operation lp_f10 6 ro 10base-t full duplex 0 b not capable of 10m full duplex operation 1 b capable of 10m full duplex operation lp_h10 5 ro 10base-t half duplex 0 b not capable of 10m operation 1 b capable of 10m operation sf 4:0 ro selector field encoding definitions table 52 anlpax registers register short name register long name offset address page number anlpa1 auto negotiation link partner ability register of port 1 225 h anlpa2 auto negotiation link partner ability register of port 2 245 h anlpa3 auto negotiation link partner ability register of port 3 265 h anlpa4 auto negotiation link partner ability register of port 4 285 h ane0 offset reset value auto negotiation expansion register of port 0 206 h 0000 h field bits type description 5hv urok 3)$8 /7 ur /313 $%/( ur 13$% /( ur 3*5& 9 ur /3$1 $%/(
data sheet 157 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx 16 bits mode registers description similar registers all anex registers have the same structure and characteristics, see ane0 . the offset addresses of the other anex registers are listed in table 53 . next page transmit register of port 0 field bits type description pfault 4 ro, lh parallel detection fault 0 b no fault detect 1 b fault has been detected lpnpable 3 ro link partner next page able 0 b link partner is not next page capable 1 b link partner is next page capable npable 2 ro next page able defaults to 0, indicating phy is not capable of next page. pgrcv 1 ro page received 0 b no new page has been received 1 b a new page has been received lpanable 0 ro link partner auto negotiation able 0 b link partner is not auto negotiable 1 b link partner is auto negotiable table 53 anex registers register short name register long name offset address page number ane1 auto negotiation expansion register of port 1 226 h ane2 auto negotiation expansion register of port 2 246 h ane3 auto negotiation expansion register of port 3 266 h ane4 auto negotiation expansion register of port 4 286 h npt0 offset reset value next page transmit register of port 0 207 h 2001 h field bits type description tnpage 15 ro transmit next page transmit code word bit 15 tmsg 13 rw transmit message page transmit code word bit 13 ur 713$ *( 5hv uz 706* uz 7$&. ur 772* uz 7)/'
samurai adm6996lc/lcx/lhx 16 bits mode registers description data sheet 158 rev. 1.31, 2005-12-05 similar registers all nptx registers have the same structure and characteristics, see npt0 . the offset addresses of the other nptx registers are listed in table 54 . link partner next page register of port 0 tack2 12 rw transmit acknowledge 2 transmit code word bit 12 ttog 11 ro transmit toggle transmit code word bit 11 tfld 10:0 rw transmit message field transmit code word bit 10..0 table 54 nptx registers register short name register long name offset address page number npt1 next page transmit register of port 1 227 h npt2 next page transmit register of port 2 247 h npt3 next page transmit register of port 3 267 h npt4 next page transmit register of port 4 287 h lpnp0 offset reset value link partner next page register of port 0 208 h 0000 h field bits type description pnpage 15 ro link partner next page receive code word bit 15 pack 14 ro link partner acknowledge receive code word bit 14 pmsgp 13 ro link partner message page receive code word bit 13 pack2 12 ro link partner acknowledge 2 receive code word bit 12 ptog 11 ro link partner toggle receive code word bit 11 pfld 10:0 ro link partner message field receive code word bit 11 field bits type description ur 313$ *( ur 3$&. ur 306* 3 ur 3$&. ur 372* ur 3)/'
data sheet 159 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx hardware, eeprom and smi interface for configuration similar registers all lpnpx registers have the same structure and characteristics, see lpnp0 . the offset addresses of the other lpnpx registers are listed in table 55 . 6 hardware, eeprom and smi interface for configuration three ways are supported to configure the setting in the adm6996lc/lcx/lhx: (1) hardware setting (2) eeprom interface (3) smi interface. users could use eeprom and smi interfaces combined with the cpu port to provide proprietary functions. four pins are needed when using these two interfaces. see figure 14 for the description. figure 14 interconnection between adm6996lc/lcx/lhx, eeprom and cpu 6.1 hardware setting the adm6996lc/lcx/lhx provides some hardware pins, where values reside on will be strapped for the default setting during the power on or reset. table 55 lpnpx registers register short name register long name offset address page number lpnp1 link partner next page register of port 1 228 h lpnp2 link partner next page register of port 2 248 h lpnp3 link partner next page register of port 3 268 h lpnp4 link partner next page register of port 4 288 h table 56 hardware setting setting name description gfcen global flow control enable. 0 b flow control capability is depended upon the register setting in corresponding eeprom register 1 b all ports flow control capability is enabled. sdio_md sdc/sdio mode selection. 0 b 16 bits mode 1 b 32 bits mode adm6996 eeprom(93c66) cpu eecs eesk edi edo
samurai adm6996lc/lcx/lhx hardware, eeprom and smi interface for configuration data sheet 160 rev. 1.31, 2005-12-05 6.2 eeprom interface the eeprom interface is provided so the users could easily configure the setting without cpu?s help. because the eeprom interface is the same as the 93c66, it also allows the cpu to write the eeprom register and renew the 93c66 at the same time. after the power up or reset (default value from the hardware pins fetched in this stage), the adm6996lc/lcx/lhx will automatically detect the presence of the eeprom by reading the address 0 in the 96c66. if the value = 4154 h , it will load all the data in the 93c66. if not, the adm6996lc/lcx/lhx will stop loading the 93c66. the user also could pull down the edo to force the adm6996lc/lcx/lhx not to load the 93c66. the 93c66 loading time is around 30ms. then cpu should drive the high-z value in the eecs, eesk and edi pins in this period if existing the cpu to read or write the registers in the adm6996lc/lcx/lhx. the eeprom interface needs only one write command to complete a ?write? operation to the adm6996lc/lcx/lhx. if users would like to update the 93c66 at the same time, then three commands, write enable, write, and write disable, are needed to complete this operation (see 93c66 spec. for the reference). user should note that the eerpom interface only allows the cpu to write the eeprom register in the adm6996lc/lcx/lhx and doesn?t support the read command. if cpu sends out the read command, then 93c66 will respond with the value inside, instead of adm6996lc/lcx/lhx. users should also note that one additional eesk cycle is needed between any continuous commands (read or write). (1) read 93c66 via the eeprom interface (index = 2, data = 1111 h ). p5_busmd[1:0] port 5 bus mode selection bit 0. p5_busmd[1:0] ,interface 00 b mii 01 b gpsi 10 b rmii 11 b reserved and not allowed. bpen recommend back-pressure in half-duplex. 0 b disable back-pressure. 1 b enable back-pressure recanen recommend auto negotiation enable. only valid for twisted pair interface. programmed this bit to 1 has no effect to fiber port. 0 b disable all tp port auto negotiation capability 1 b enable all tp port auto negotiation capability xoven cross over enable. only available in tp interface. 0 b disable 1 b enable led_mode enable mac to choose led display mode. 0 b single color led 1 b dual color led table 56 hardware setting (cont?d) setting name description 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 0 d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 start opcode eeprom adress (index) dummy eecs(cpu) eesk(cpu) edi (cpu) edo (93c46) one more eesk is needed eeprom read operation data
data sheet 161 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx hardware, eeprom and smi interface for configuration (2) write eeprom registers in the adm6996lc/lcx/lhx (index = 2, data =16?h2222). 6.3 smi interface the smi consists of two pins, management data clock (eesk) and management data input/output (edi). the adm6996lc/lcx/lhx is designed to support an eesk frequency up to 25 mhz. the edi pin is bi-directional and may be shared with other devices. eecs pin is needed to pull low if eeprom interface is also used. the edi pin requires a 1.5 k ? pull-up which, during idle and turnaround periods, will pull edi to a logic one state. adm6996lc/lcx/lhx requires a single initialization sequence of 32 bits of preamble following power- up/hardware reset. the first 32 bits are preamble consisting of 32 contiguous logic one bits on edi and 32 corresponding cycles on eesk. following preamble is the start-of-frame field indicated by a <01 b > pattern. the next field signals the operation code (op): <10 b > indicates read from management register operation, and <01 b > indicates write to management register operation. the next field is the management register address. it is 10 bits wide and the most significant bit is transferred first. during read operation, a 2-bit turn around (ta) time spacing between the register address field and data field is provided for the edi to avoid contention. following the turnaround time, a 16-bit data stream is read from or written into the management registers of the adm6996lc/lcx/lhx. (a) preamble suppression the smi of adm6996lc/lcx/lhx supports a preamble suppression mode. the adm6996lc/lcx/lhx requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset. this requirement is generally met by pulling-up the resistor of edi while the adm6996lc/lcx/lhx will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required. when adm6996lc/lcx/lhx detects that there is address match, then it will enable read/write capability for external access. when address is mismatched, then adm6996lc/lcx/lhx will tri-state the edi pin. (b) read switch register via smi interface (offset hex = 10?h2, data = 16?h2600) (c) write switch register via smi interface (offset hex = 10?h180, data = 16?h1300) 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 start opcode eeprom adress (index) eecs(cpu) eesk(cpu) edi (cpu) one more eesk is needed eeprom write operation d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data eesk edi(cpu) edi(adm6996i/m) z 0 1 1 0 0 0 0 0 0 0 0 0 1 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (read) register address (10'h2 in this example) ta register data (16'h2600 in this example) ~ ~ smi read operation one mor e eesk is needed
samurai adm6996lc/lcx/lhx hardware, eeprom and smi interface for configuration data sheet 162 rev. 1.31, 2005-12-05 table 57 (d) the pin type of eecs, eesk, edi and edo during the operation pin name reset operation load eeprom write operation read operation eecs input output input input eesk input output input input edi input output input input/output edo input input input input eesk edi (cpu) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (write) register address (10'h180 in this example) ta register data (16'h1300 in this example) 0 ~ ~ smi write operation one mor e eesk is needed
data sheet 163 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7 electrical specification 7.1 tx/fx interface 7.1.1 tp interface figure 15 tp interface transformer requirements: ?tx/rx rate 1:1 ? tx/rx central tap connect together to vcca2 users can change the tx/rx pin for easy layout but do not change the polarity. adm6996lc/lcx/lhx supports auto polarity on the receiving side. txp txn adm6996 rxp rxn 49.9 49.9 49.9 49.9 0.01u 0.01u 1:1 1:1 auto-mdix x'fmr 1 2 3 4 5 6 7 8 rj-45 vcca2 75 75 75 0.1u hi-pot cap r1 r2 c1
samurai adm6996lc/lcx/lhx electrical specification data sheet 164 rev. 1.31, 2005-12-05 7.1.2 fx interface figure 16 fx interface 7.2 dc characterization table 58 power consumption parameter symbol values unit note / test condition min. typ. max. power consumption when all twisted pair ports are linked at 100 mbit/s. p 100m_5tp ? 980 ? mw under eeprom register 29 h = c000 h , and 30 h = 985 h power consumption when all twisted pair ports are linked at 10 mbit/s (include transformer). p 10m_5tp ? 1450 ? mw under eeprom register 29 h = c000 h , and 30 h = 985 h power consumption when all twisted pair ports are disconnected. p dis_5tp ? 500 ? mw under eeprom register 29 h = c000 h , and 30 h = 985 h txp txn adm6996 rxp rxn 69 1 gnd_rx 2 rd+ 3 rd- 4 sd 5 vcc_rx 6 vcc_tx 7 td- 8 td+ 9 gnd_tx 3.3v fiber transceiver 69 182 182 127 127 83 83 +3.3v +3.3v 83 127 +3.3v sd sd vcc(3.3) vcc(3.3)
data sheet 165 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 59 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. 3.3 v power supply for i/o pad v cc3o 2.97 3.3 3.63 v ? 3.3 v power supply for bias circuit v ccbs 2.97 3.3 3.63 v ? 3.3 v power supply for a/d converter v ccad 2.97 3.3 3.63 v ? 1.8 v power supply for line driver v cca2 1.62 1.8 1.98 v ? 1.8 v power supply for pll v ccpll 1.62 1.8 1.98 v ? 1.8 v power supply for digital core v ccik 1.62 1.8 1.98 v ? input voltage v in -0.3 ? v cc3o + 0.3 v? output voltage v out -0.3 ? v cc3o + 0.3 v? maximum current for 3.3 v power supply i 3.3vmax ??100ma? maximum current for 1.8 v power supply (include transformer) i 1.8vmax ??800ma? storage temperature t stg -55 ? 155 c ? esd rating esd 1.0??kv? table 60 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. 3.3 v power supply for i/o pad v cc3o 3.135 3.3 3.465 v ? 3.3 v power supply for bias circuit v ccbs 3.135 3.3 3.465 v ? 3.3 v power supply for a/d converter v ccad 3.135 3.3 3.465 v ? 1.8 v power supply for line driver v cca2 1.71 1.8 1.89 v ? 1.8 v power supply for pll v ccpll 1.71 1.8 1.89 v ? 1.8 v power supply for digital core v ccik 1.71 1.8 1.89 v ? input voltage v in 0? v cc v? junction operating temperature t j 025115c?
samurai adm6996lc/lcx/lhx electrical specification data sheet 166 rev. 1.31, 2005-12-05 7.3 ac characterization 7.3.1 xtal/osc timing figure 17 xtal/osc timing table 61 dc electrical characteristics for 3.3 v operation 1) 1) under v cc3o = 2.97v ~ 3.63 v, t j = 0 c ~ 115 c parameter symbol values unit note / test condition min. typ. max. input low voltage v il ? ? 0.8 v ttl input high voltage v ih 2.0??vttl output low voltage v ol ? ? 0.4 v ttl output high voltage v oh 2.4??vttl input pull-up/down resistance r i ?50?k ? v il = 0 v or v ih = v cc3o table 62 xtal/osc timing parameter symbol values unit note / test condition min. typ. max. xi/osci clock period t _xi_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? xi/osci clock high t _xi_hi 14 20.0 ? ns ? xi/osci clock low t _xi_lo 14 20.0 ? ns ? xi/osci clock rise time, v il (max) to v ih (min.) t _xi_rise ??4ns? xi/osci clock fall time, v ih (min.) to v il (max) t _xi_fall ??4ns? t xi_rise t xi_fall t xi_hi t xi_lo t xi_per v il-xi v ih-xi
data sheet 167 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7.3.2 power on reset figure 18 power on reset timing 7.3.3 eeprom interface timing figure 19 eeprom interface timing table 63 power on reset timing parameter symbol values unit note / test condition min. typ. max. rst low period t rst 100??ms? start of idle pulse width t conf 100??ns? table 64 eeprom interface timing parameter symbol values unit note / test condition min. typ. max. eesk period t esk ? 5120 ? ns ? eesk low period t eskl 2550 ? 2570 ns ? eesk high period t eskh 2550 ? 2570 ns ? tconf trst trst 0us 50us 100us 150us rst* all configuration pins terdh terds tewdd tesk tesk teskl teskl teskh teskh 0us 10us 20us 30us eecs eesk eedo eedi
samurai adm6996lc/lcx/lhx electrical specification data sheet 168 rev. 1.31, 2005-12-05 7.3.4 10base-tx mii input timing figure 20 10base-tx mii input timing eedi to eesk rising setup time t erds 10??ns? eedi to eesk rising hold time t erdh 10??ns? eesk falling to eedo output delay time t ewdd ??20ns? table 65 10base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck ? 400 ? ns ? mii_rxclk low period t ckl 180 ? 220 ns ? mii_rxclk high period t ckh 180 ? 220 ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising setup t rxs 10??ns? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising hold t rxh 10??ns? table 64 eeprom interface timing (cont?d) parameter symbol values unit note / test condition min. typ. max. 0ns 2000ns 1000ns tck tck mii_rxclk tckh tckh tckl tckl trxs trxh mii_rxdv mii_rxd mii_crs
data sheet 169 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7.3.5 10base-tx mii output timing figure 21 10base-tx mii output timing table 66 10-base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck ? 400 ? ns ? mii_txclk low period t ckl 180 ? 220 ns ? mii_txclk high period t ckh 180 ? 220 ns ? mii_txd, mii_txen tomii_txclk rising output delay t txod 0?25ns? 0ns 500ns 1000ns 2000ns 1500ns 2500ns mii_txen mii_txd mii_txclk tckh tckh tckl tckl tck tck ttxod
samurai adm6996lc/lcx/lhx electrical specification data sheet 170 rev. 1.31, 2005-12-05 7.3.6 100base-tx mii input timing figure 22 100base-tx mii input timing table 67 100base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck ?40?ns? mii_rxclk low period t ckl 18 ? 22 ns ? mii_rxclk high period t ckh 18 ? 22 ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising setup t rxs 10??ns? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising hold t rxh 10??ns? 0ns 100ns 200ns tck tck mii_rxclk tckh tckh tckl tckl trxs trxh mii_rxdv mii_rxd mii_crs
data sheet 171 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7.3.7 100base-tx mii output timing figure 23 100base-tx mii output timing 7.3.8 rmii refclk input timing figure 24 rmii refclk input timing table 68 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck ?40?ns? mii_txclk low period t ckl 18 ? 22 ns ? mii_txclk high period t ckh 18 ? 22 ns ? mii_txd, mii_txen tomii_txclk rising output delay t txod 0?25ns? 0ns 50ns 100ns 200ns 150ns 250ns mii_txen mii_txd mii_txclk tckh tckh tckl tckl tck tck ttxod t in50_rise t in50_fall t in50_hi t in50_lo t in50_per v il-rmii v ih-rmii
samurai adm6996lc/lcx/lhx electrical specification data sheet 172 rev. 1.31, 2005-12-05 7.3.9 rmii refclk output timing figure 25 rmii refclk output timing table 69 rmii refclk input timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t in50_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? refclk clock high t in50_hi 14 20.0 ? ns ? refclk clock low t in50_lo 14 20.0 ? ns ? refclk clock rise time, v il (max) to v ih (min.) t in50_rise ??2ns? refclk clock fall time, v ih (min.) to v il (max) t in50_fall ??2ns? table 70 rmii refclk output timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t out50_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? refclk clock high t out50_hi 14 20.0 26 ns ? refclk clock low t out50_lo 14 20.0 26 ns ? refclk clock rise time, v ol (max) to v oh (min.) t out50_rise ??2ns? refclk clock fall time, v oh (min.) to v ol (max) t out50_fall ??2ns? refclk clock jittering (p-p) t out50_jit ?0.15?ns? t out50_rise t out50_fall t out50_hi t out50_lo t out50_per v ol-rmii v oh-rmii
data sheet 173 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7.3.10 reduce mii timing figure 26 reduce mii timing (1 of 2) figure 27 reduce mii timing (2 of 2) table 71 reduce mii timing parameter symbol values unit note / test condition min. typ. max. rmii_refclk period t ck ?20?ns? rmii_refclk low period t ckl ?10?ns? rmii_refclk high period t ckh ?10?ns? txen, txd to refclk rising setup time t txs 4??ns? txe, txd to refclk rising hold time t txh 2??ns? csrdv, rxd to refclk rising setup time t rxs 4?? ? crsdv, rxd to refclk rising hold time t rxh 2?? ? ttxh ttxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_txen txd[1:0] trxh trxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_crsdv rxd[1:0]
samurai adm6996lc/lcx/lhx electrical specification data sheet 174 rev. 1.31, 2005-12-05 7.3.11 gpsi (7-wire) input timing figure 28 gpsi (7-wire) input timing table 72 gpsi (7-wire) input timing parameter symbol values unit note / test condition min. typ. max. gpsi_rxclk period t ck ? 100 ? ns ? gpsi_rxclk low period t ckl 40 ? 60 ns ? gpsi_rxclk high period t ckh 40 ? 60 ns ? gpsi_rxd, gpsi_crs/col to gpsi_rxclk rising setup time t rxs 10??ns? gpsi_rxd, gpsi_crs/col to gpsi_rxclk rising holdtime t rxh 10??ns? 0ns 500ns 250ns gpsi_crs/col gpsi_rxd gpsi_rxclk tckh tckh tckl tckl tck tck trxh trxs
data sheet 175 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx electrical specification 7.3.12 gpsi (7-wire) output timing figure 29 gpsi (7-wire) output timing 7.3.13 sdc/sdio timing figure 30 sdc/sdio timing table 73 gpsi (7-wire) output timing parameter symbol values unit note / test condition min. typ. max. gpsi_txclk period t ck ? 100 ? ns ? gpsi_txclk low period t ckl 40 ? 60 ns ? gpsi_txclk high period t ckh 40 ? 60 ns ? gpsi_txclk rising togpsi_txen/gpsi_txd output delay t od 50 ? 70 ns ? 0ns 500ns 250ns tckh tckh tckl tckl tck tck tod gpsi_txclk gpsi_txd gpsi_txen tsdh tsds tsdc tsdcl tsdcl tsdch tsdc tsdch 0ns 25ns 50ns 75n s 100 ns sdc sdio
samurai adm6996lc/lcx/lhx electrical specification data sheet 176 rev. 1.31, 2005-12-05 table 74 sdc/sdio timing parameter symbol values unit note / test condition min. typ. max. sdc period t ck 20??ns? sdc low period t ckl 10??ns? sdc high period t ckh 10??ns? sdio to sdc rising setup time on read/write cycle t sds 4??ns? sdio to sdc rising hold time on read/write cycle t sdh 2??ns?
data sheet 177 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx package outlines 8 package outlines figure 31 p-pqfp-128 outside dimension 8.1 package information product name product type package 6-port 10/100 mbit/s single chip ethernet switch controller samurai, adm6996lc/lcx/lhx- ac-t-1), version ac p-pqfp-128
samurai adm6996lc/lcx/lhx terminology data sheet 178 rev. 1.31, 2005-12-05 terminology b ber bit error rate c cfi canonical format indicator col collision crc cyclic redundancy check crs carrier sense cs chip select d da destination address di data input do data output e edi eeprom data input edo eeprom data output eecs eeprom chip select eesk eeprom clock esd end of stream delimiter f fefi far end fault indication fet field effect transistor flp fast link pulse g gnd ground gpsi general purpose serial interface i ipg inter-packet gap l lfsr linear feedback shift register m mac media access controller mdix mdi crossover mii media independent interface n nrzi non return to zero inverter nrz non return to zero p pcs physical coding sub-layer phy physical layer pll phase lock loop pma physical medium attachment
data sheet 179 rev. 1.31, 2005-12-05 samurai adm6996lc/lcx/lhx terminology pmd physical medium dependent q qos quality of service qfp quad flat package r rst reset rxclk receive clock rxd receive data rxdv receive data valid rxer receive data errors rxn receive negative (analog receive differential signal) rxp receive positive (analog receive differential signal) s sa source address soho small office home office ssd start of stream delimiter sqe signal quality error t tos type of service tp twisted pair ttl transistor logic txclk transmission clock txd transmission data txen transmission enable txn transmission negative txp transmission positive
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